As the size of datasets and neural network models increases, automatic parallelization methods for models have become a research hotspot in recent years. The existing auto-parallel methods based on machine learning or...
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As the size of datasets and neural network models increases, automatic parallelization methods for models have become a research hotspot in recent years. The existing auto-parallel methods based on machine learning or...
As the size of datasets and neural network models increases, automatic parallelization methods for models have become a research hotspot in recent years. The existing auto-parallel methods based on machine learning or graph algorithms still have issues with search efficiency and applicability. This paper proposes an automatic parallel method based on a dual-population genetic algorithm, TGA, which transforms model partitioning and placement into an integer linear programming problem and constructs a cost model to evaluate the solution. The solution space is built using the neural network’s dataflow graph and device cluster’s topology, and the dual-population genetic algorithm is used to search for the optimal model parallel strategy. Experiments with various models show that the proposed method can improve single-step execution time by up to 42% compared to the Baechi method and up to 37.7% compared to the Hierarchical method.
As 5G networks rolling out in many different countries nowadays, the time has come to investigate how to upgrade and expand them towards 6G, where the latter is expected to realize the interconnection of everything as...
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Researching post-quantum cryptography has been an important task in cryptography. The section finding problem on algebraic surfaces (AS-SFP) is considered to be intractable also after building quantum computers. Thus ...
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ISBN:
(纸本)9781509026562
Researching post-quantum cryptography has been an important task in cryptography. The section finding problem on algebraic surfaces (AS-SFP) is considered to be intractable also after building quantum computers. Thus AS-SFP is used as a basis of the security of the Algebraic Surface Cryptosystem (ASC), which is a candidate of post-quantum cryptosystems, and it is important for designing parameters which make ASC secure to estimate the complexity of AS-SFP. Solving AS-SFP is reduced to solving certain multivariate equation systems (section equation systems) of high degrees, and one can solve such equation systems by using the Grobner basis technique. Although estimating the complexity of computing a Grobner basis associated with an equation system is difficult in general, it becomes easy if the equation system is semi-regular. In this paper, we experimentally estimate the complexity of AS-SFP. From our experimental results, although we see that section equation systems do not become semi-regular in most cases for small parameters, we can infer parameters closely related to the difficulty of computing Grobner bases associated with section equation systems. According to our inference, we estimate the complexity of AS-SFP and parameters which make ASC 128-bit security against the attack by the Grobner basis technique. We also consider a brute-force attack against AS-SFP and conjecture that the brute-force attack is more efficient than the attack by the Grobner basis technique. Finally, we estimate parameters and sizes of public keys such that ASC has 128-bit security against the brute-force attack. Its size (876 bits) is much smaller than sizes of public keys in other efficient candidates of PQC.
In view of the introduction of computer technologies into social infrastructure, computersecurity is rapidly emerging as a major real-world problem. Since control devices are left in physically insecure fields, the r...
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In view of the introduction of computer technologies into social infrastructure, computersecurity is rapidly emerging as a major real-world problem. Since control devices are left in physically insecure fields, the r...
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In view of the introduction of computer technologies into social infrastructure, computersecurity is rapidly emerging as a major real-world problem. Since control devices are left in physically insecure fields, the risk of physical attack is a greater concern than in the case of data center systems. In addition, non-volatile main memory technology may extend the threat because an attacker can easily manipulate and retrieve data stored in the memory. Much research has been done with a view to realizing secure processors with integrity tree verification, but no secure processor product with MMU capability has been commercialized so far. In this paper, TREBIVE, a TREe-Based Integrity Verification Environment, is proposed. It offers VMM-based memory integrity and confidentiality protection for existing COTS processors. A prototype VMM is constructed using ARM Cortex-A15 processors and quantitative analysis is performed using the Linux environment. The result shows a considerable amount of overhead, which is a concern. However, the results of experiments on SQLite queries support the view that the proposed method offers quicker response than whole DB image verification on existing systems. A target system model to mitigate the overhead is also proposed, in order to support robust disconnected operation of field devices.
Reliable multicast protocols are an important class of protocols for reliably disseminating information from a sender to multiple receivers in the face of node and link failures. A tree-based reliable multicast protoc...
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Reliable multicast protocols are an important class of protocols for reliably disseminating information from a sender to multiple receivers in the face of node and link failures. A tree-based reliable multicast protocol (TRAM) provides scalable reliable multicast by grouping receivers in hierarchical repair groups and using a selective acknowledgment mechanism. We present an improvement to TRAM to minimize the resource utilization at intermediate hosts and to localize the effect of slow or malicious receivers on normal receivers. We present an evaluation of TRAM and TRAM++ on a campus-wide WAN without errors and with message errors. The evaluation brings out that, given a constraint on the buffer availability at intermediate hosts, TRAM++ can tolerate the constraint at the expense of increasing the end-to-end latency for the normal receivers by only 3.2% compared to TRAM in error-free cases. When slow or faulty receivers are present, TRAM++ is able to provide the same uninterrupted quality of service to the normal nodes while localizing the effect of the faulty ones without incurring any additional memory overhead.
作者：
ZITZMAN, LHFALATKO, SMPAPACH, JLDr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group
Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department
Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department
Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin
This paper sets forth computersystemsarchitecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis comp...
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This paper sets forth computersystemsarchitecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computersystemsarchitecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computersystems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computerarchitecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computerarchitecture to a general architecture for the future. The proposed computersystemsarchitecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st
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