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IEEE International Symposium on Circuits and systems

作者： Winnie Thomas Suryakant Toraskar Virendra Singh Computer Architecture and Dependable Systems Laboratory Dept. of Electrical Engineering Indian Institute of Technology Bombay India

ISBN: (纸本)9781728192017;9781728192024

Massively parallel processors such as graphics processing units (GPUs) often face the challenge of resource underutilization due to varying resource proclivity of workloads. Running multiple applications on a GPU has been an efficient and known alternative to mitigate underutilization. This paper proposes a multi-application oriented framework that carries out dynamic optimizations based on the operational intensities of various applications. Our framework analyzes applications based on operational intensities to identify their bottleneck resources using Roofline model. We demonstrate that the proposed optimizations improve the utilization and system-wide throughput of the GPU co-running applications with irregular resource demands. The dynamic optimizations improve the performance by 14.8% on average and up to 72.4% over a state-of-the-art spatial multitasking technique.

关键词： Heuristic algorithms Graphics processing units Throughput Multitasking Resource management Optimization Faces

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Towards energy-aware software-based fault tolerance in real-time systems

Towards energy-aware software-based fault tolerance in real-...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： O.S. Unsal I. Koren C.M. Krishna Architecture and Real-Time Systems Laboratory Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

Many real-time systems employed in defense, space, and consumer applications have power constraints and high reliability requirements. In this paper, we focus on the relationship between fault tolerance techniques and energy consumption. In particular, we establish the energy efficiency of Application Level Fault Tolerance (ALFT) over other software-based fault tolerance methods. We then develop sensible energy-aware heuristics for ALFT schemes. The heuristics yield up to 40% energy savings.

关键词： Fault tolerant systems Real time systems Fault tolerance Redundancy Application software Power system reliability Permission Scheduling computer architecture Laboratories

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TraceTracker: Hardware/software co-evaluation for large-scale I/O workload reconstruction

arXiv

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arXiv 2017年

作者： Kwon, Miryeong Zhang, Jie Park, Gyuyoung Choi, Wonil Donofrio, David Shalf, John Kandemir, Mahmut Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory School of Integrated Technology Yonsei University Pennsylvania State University Lawrence Berkeley National Laboratory

Block traces are widely used for system studies, model verifications, and design analyses in both industry and academia. While such traces include detailed block access patterns, existing trace-driven research unfortunately often fails to find true-north due to a lack of runtime contexts such as user idle periods and system delays, which are fundamentally linked to the characteristics of target storage hardware. In this work, we propose TraceTracker, a novel hardware/software co-evaluation method that allows users to reuse a broad range of the existing block traces by keeping most their execution contexts and user scenarios while adjusting them with new system information. Specifically, our TraceTracker's software evaluation model can infer CPU burst times and user idle periods from old storage traces, whereas its hardware evaluation method remasters the storage traces by interoperating the inferred time information, and updates all inter-arrival times by making them aware of the target storage system. We apply the proposed co-evaluation model to 577 traces, which were collected by servers from different institutions and locations a decade ago, and revive the traces on a high-performance flash-based storage array. The evaluation results reveal that the accuracy of the execution contexts reconstructed by TraceTracker is on average 99% and 96% with regard to the frequency of idle operations and the total idle periods, respectively. Copyright © 2017, The Authors. All rights reserved.

关键词： computer software selection and evaluation

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Automatic instruction set extension and utilization for embedded processors

Automatic instruction set extension and utilization for embe...

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International Conference on Application Specific systems (ASAP), architectures and Processors

作者： A. Peymandoust L. Pozzi P. Ienne G. De Micheli Computer Systems Laboratory University of Stanford Stanford CA USA Processor Architecture Laboratory Swiss Federal Institute of Technology Lausanne Switzerland

There is a growing demand for application-specific embedded processors in system-on-a-chip designs. Current tools and design methodologies often require designers to manually specialize the processor based on an application. Moreover, the use of the new complex instructions added to the processor is often left to designers' ingenuity. We present a solution that automatically groups dataflow operations in the application software as potential new complex instructions. The set of possible instructions is then automatically used for code generation combined with high-level arithmetic optimizations using symbolic algebra. Symbolic arithmetic manipulations provide a novel and effective method for instruction selection that is necessary due to the complexity of the automatically identified instructions. We have used our methodology to automatically add new instructions to Tensilica processors for a set of examples. Our results show that our tools improve designers productivity and efficiently specialize an embedded processor for the given application such that the execution time is greatly improved.

关键词： Application specific processors Application software Design methodology Time to market Laboratories computer architecture Arithmetic Algebra Costs Embedded system

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TREBIVETM: A TREe Based Integrity Verification Environment for Non-volatile Memory System

TREBIVETM: A TREe Based Integrity Verification Environment f...

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Pacific Rim International Symposium on Dependable Computing

作者： Mikio Hashimoto Naoko Yamada Jun Kanai Computer Architecture & Security Systems Laboratory Corporate Research & Development Center Toshiba Saiwai-ku Kawasaki Japan

In view of the introduction of computer technologies into social infrastructure, computer security is rapidly emerging as a major real-world problem. Since control devices are left in physically insecure fields, the risk of physical attack is a greater concern than in the case of data center systems. In addition, non-volatile main memory technology may extend the threat because an attacker can easily manipulate and retrieve data stored in the memory. Much research has been done with a view to realizing secure processors with integrity tree verification, but no secure processor product with MMU capability has been commercialized so far. In this paper, TREBIVE, a TREe-Based Integrity Verification Environment, is proposed. It offers VMM-based memory integrity and confidentiality protection for existing COTS processors. A prototype VMM is constructed using ARM Cortex-A15 processors and quantitative analysis is performed using the Linux environment. The result shows a considerable amount of overhead, which is a concern. However, the results of experiments on SQLite queries support the view that the proposed method offers quicker response than whole DB image verification on existing systems. A target system model to mitigate the overhead is also proposed, in order to support robust disconnected operation of field devices.

关键词： Encryption Operating systems Computational modeling Load modeling Concrete Loading

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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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Dynamic topologies for particle swarms 7

Dynamic topologies for particle swarms

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7th International Joint Conference on Computational Intelligence, IJCCI 2015

作者： Fernandes, Carlos M. Laredo, J.L.J. Merelo, J.J. Cotta, C. Rosa, A.C. LARSyS: Laboratory for Robotics and Systems in Engineering and Science University of Lisbon Lisbon Portugal Department of Architecture and Computer Technology University of Granada Granada Spain Departamento de Lenguages y Ciencias de la Computación University of Malaga Malaga Spain

ISBN: (纸本)9783662535240

The Particle Swarm Optimization (PSO) algorithm is a population-based metaheuristics in which the individuals communicate through decentralized networks. The network can be of many forms but traditionally its structure is predetermined and remains fixed during the search. This paper investigates an alternative approach. The particles are positioned on a 2-dimensional grid of nodes. During the run, they move through the network according to simple rules, while interacting with each other using signs that they leave on the nodes. The links between the particles – and consequently the information flow – are then defined at each time step by the position of the particle on the grid. As a result, each particle’s set of neighbors and connectivity degree varies during the search progress. The particles can move randomly or instead track signs left by other particles on the grid. In this paper, after a formal description of the general model, two different strategies (random and sign-based) are tested and compared to standard topologies on unimodal and multimodal functions, including a rotated and a shifted function with noise from the CEC benchmark. The experiments demonstrate that the dynamics provided by the proposed structure results in a more consistent and stable performance throughout the test set. The working mechanisms of the model are simple and easy to implement. © Springer-Verlag Berlin Heidelberg 2016.

关键词： Topology

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Virtualizing modern high-speed interconnection networks with performance and scalability

Virtualizing modern high-speed interconnection networks with...

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作者： Li, Bo Huo, Zhigang Zhang, Panyong Meng, Dan National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542201

As one of the most important enabling technologies of cloud computing, virtualization brings to HPC good manageability, online system maintenance, performance isolation and fault isolation. Furthermore, previous study on VMM-bypass I/O that virtualizes OS-bypass networks (e.g. Infini- Band) relieved the worry of performance degradation coming along with virtualization. In this paper, we address the scalability challenges imposed upon OS-bypass networks under virtualized environments. The eXtended Reliable Connection (XRC) transport, proposed in modern high-speed interconnection networks to address the scalability problem in large scale applications, would not work in virtualized environments. To solve the problem, we propose VM-proof XRC design to eliminate the scalability gap between virtualized and native environments. Prototype evaluation shows that the virtualization of modern high-speed interconnection networks could get the same raw performance and scalability as in native non-virtualized environment with our VM-proof XRC design. The connection memory scalability shows a potential of 16 times improvement on virtualized clusters composed of 16-core nodes. © 2010 IEEE.

关键词： Scalability

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A study of memory system performance of multimedia applications 01

A study of memory system performance of multimedia applicati...

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Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems

作者： Sohum Sohoni Rui Min Zhiyong Xu Yiming Hu Operating Systems and Computer Architecture Laboratory Department of Electrical & Computer Engineering and Computer Science P.O. Box 210030 University of Cincinnati Cincinnati OH

ISBN: (纸本)9781581133349

Multimedia applications are fast becoming one of the dominating workloads for modern computer systems. Since these applications normally have large data sets and little data-reuse, many researchers believe that they have poor memory behavior compared to traditional programs, and that current cache architectures cannot handle them well. It is therefore important to quantitatively characterize the memory behavior of these applications in order to provide insights for future design and research of memory systems. However, very few results on this topic have been published. This paper presents a comprehensive research on the memory requirements of a group of programs that are representative of multimedia applications. These programs include a subset of the popular MediaBench suite and several large multimedia programs running on the Linux, Windows NT and Tru UNIX operating systems. We performed extensive measurement and trace-driven simulation experiments. We then compared the memory utilization of these programs to that of SPECint95 applications. We found that multimedia applications actually have better memory behavior than SPECint95 programs. The high cache hit rates of multimedia applications can be contributed to the following three factors. Most multimedia applications apply block partitioning algorithms to the input data, and work on small blocks of data that easily fit into the cache. Secondly, within these blocks, there is significant data reuse as well as spatial locality. The third reason is that a large number of references generated by multimedia applications are to their internal data structures, which are relatively small and can also easily fit into reasonably-sized caches.

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The producing system

The producing system

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15th Annual International Symposium of the International Council on systems Engineering, INCOSE 2005

作者： Paul, Arthur Yerace, Gary Department of Systems and Computer Science College of Engineering Architecture and Computer Sciences Howard University 2300 Sixth Street NW Washington DC 20059 United States Computational and Information Sciences Directorate US Army Research Laboratory 2800 Powder Mill Road Adelphi MD 20783-1197 United States

ISBN: (纸本)9781622769285

This paper discusses the importance of the enabling resources (otherwise identified as enabling capacity or enabling capabilities) to the successful development of systems. It proposes the Producing System as a mechanism for planning, acquiring, deploying and ma aging these enabling resources as a system of interest, in addition to the delivered or required system, in the system development process. ©2005 by Arthur Paul and Gary Yerace. Published and used by INCOSE with permission.

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