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A Logarithmic-Complexity Algorithm for Nearest Neighbor Classification Using Layered Range Trees

Intelligent Information Management 2012年第2期4卷 39-43页

作者： Ibrahim Al-Bluwi Ashraf Elnagar Department of Computer Science University of Sharjah Sharjah UAE Laboratory for Analysis and Architecture of Systems (LAAS-CNRS) Universitt’e de Toulouse Toulouse France

Finding Nearest Neighbors efficiently is crucial to the design of any nearest neighbor classifier. This paper shows how Layered Range Trees (LRT) could be utilized for efficient nearest neighbor classification. The presented algorithm is robust and finds the nearest neighbor in a logarithmic order. The proposed algorithm reports the nearest neighbor in , where k is a very small constant when compared with the dataset size n and d is the number of dimensions. Experimental results demonstrate the efficiency of the proposed algorithm.

关键词： Nearest Neighbor Classifier Range Trees Logarithmic Order

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An efficient parallel architecture for ray-tracing

An efficient parallel architecture for ray-tracing

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作者： Nery, Alexandre S. Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microeletronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Do Rio de Janeiro Rio de Janeiro RJ Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade Do Estado Do Rio de Janeiro Rio de Janeiro RJ Brazil

Real time rendering of three-dimensional scenes in high photorealistic details is a hard task, such as in the ray tracing rendering algorithm. In general, the performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. However, parallel implementations of ray tracing have been enabling reasonable real time performance, as the algorithm is embarrassingly parallel. Thus, a custom parallel design in hardware is likely to achieve an even higher performance. In this paper, we propose a hardware parallel architecture capable of dealing with the main desirable features of ray tracing, such as shadows and reflection effects, imposing low area cost and a promising rendering performance. Such architecture, called GridRT, is based on the Uniform Grid acceleration structure and is intended to deliver massive parallelism through parallel ray-triangle intersection tests as well as parallel processing of many rays. A hardware implementation of the proposed architecture is presented, together with some performance results and resources requirements. The rendering is reduced by 80% using a grid configuration of eight processing elements. © Springer Science+Business Media, LLC 2011.

关键词： Field programmable gate arrays (FPGA)

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A sensor positioning algorithm for the EMMON large scale Wireless Sensor Network architecture

A sensor positioning algorithm for the EMMON large scale Wir...

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IEEE International Conference on Industrial Technology (ICIT)

作者： Theodoros Fronimos Loukas Petrou George Hassapis Department of Electrical and Computer Engineering Laboratory of Computer Systems Architecture Aristotle University of Thessaloniki Thessaloniki Greece Department of Electrical and Computer Engineering Aristotle University of Thessaloniki Thessaloniki Greece

In this paper a sensor positioning scheme is proposed for the EMMON architecture of Wireless Sensor Networks (WSN). This is a recently developed new multi - tiered hierarchical structure imposing the need for a distributed, low - complexity positioning algorithm. In this work we developed an integrated positioning scheme which involves an on-line calibration phase and a subsequent assessment of the parameters of a fuzzy inference system used to generate distance approximations based on RSSI values. In the calibration phase a sensor node is placed arbitrarily in a number of known positions and collects RSSI measurements from all anchor nodes. A data set consisting of RSSI values vs. distance is created and is used as training data set of the fuzzy inference system. Finally experimental results are presented which show the improvement achieved in the accuracy of the proposed scheme against other range-based schemes.

关键词： Wireless sensor networks computer architecture Internet Protocols Estimation Position measurement

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A differential public PUF design for lightweight authentication 16

A differential public PUF design for lightweight authenticat...

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2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2021 and 16th Conference on PhD Research in Microelectronics and Electronics, PRIME 2021

作者： Duan, Shengyu Sai, Gaole School of Computer Engineering and Science Shanghai University Shanghai200444 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Guangdong Provincial Key Lab of Robotics and Intelligent System Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences China CAS Key Laboratory of Human-Machine Intelligence-Synergy Systems Shenzhen Institutes of Advanced Technology China

ISBN: (纸本)9783800755899

Physical Unclonable Functions (PUFs) have emerged as a promising primitive to provide a hardware keyless security mechanism for integrated circuit applications. Public PUFs (PPUFs) address the crucial PUF vulnerability of requiring databases to store the secrete reference information. This paper investigates one of the PPUF families, differential PPUF (dPPUF), which exploits complexly interacted logic to create time gap between actual execution and simulation, and to prevent simulation attacks. Conventional dPPUFs have high costs. We observe the repressers have large impact on simulation time, but take a great proportion in current dPPUF structure. We thereby present a represser network with specially designed interconnection and shared logic, to maintain a high circuit complexity and to reduce the area cost. We show the proposed dPPUF has similar resilience over simulation attacks as the conventional design. Area cost can be reduced by up to 44%, and thus the proposed design can be used for lightweight authentication. © VDE VERLAG GMBH.

关键词： Authentication

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Early Experiences with Write-Write Design of NFS over RDMA

Early Experiences with Write-Write Design of NFS over RDMA

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International Conference on Networking, architecture, and Storage (NAS)

作者： Bo Li Panyong Zhang Zhigang Huo Dan Meng National Research Center for Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China National Research Center for Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences China

The network file system (NFS) protocol, as the de facto standard for sharing files in a distributed environment, has deployed Infiniband as the underlying transport of sunRPC, namely NFS over RDMA. In the current Read-Write design of NFS over RDMA, NFS write performance is limited for not fully utilizing the features of Infiniband. In this paper, we take on the challenge of enhancing the write performance of NFS. We propose and evaluate a new design of sunRPC over RDMA, namely Write-Write design. To guarantee the security of our design, we propose an HCA-based memory protection extension of Infiniband. Evaluations show that our Write-Write design increases the kernel-to-kernel RPC bandwidth by 15~27%. In real disk test, our Write-Write design gains 15%~22% in multi-client benchmarks compared with the Read-Write design.

关键词： Security Protection Bandwidth Scalability computer architecture computer networks Distributed computing File systems Benchmark testing Protocols

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Diffuse axonal injury lesion segmentation using contouring algorithm

Diffuse axonal injury lesion segmentation using contouring a...

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21st International Conference on computer Graphics and Vision, GraphiCon'2011

作者： Senyukova, Olga V. Galanine, Valeriy E. Krylov, Andrey S. Petraikin, Alexey V. Akhadov, Tolibdjon A. Sidorin, Sergey V. Department of Computer Systems Architecture Faculty of Computational Mathematics and Cybernetics Lomonosov Moscow State University Moscow Russia Faculty of Computational Mathematics and Cybernetics Lomonosov Moscow State University Moscow Russia Laboratory of Mathematical Methods of Image Processing CMC MSU Russia Moscow Russia

Diffuse axonal injury (DAI) is a common type of brain damage induced by trauma. Accurate detection and quantification of DAI lesions is essential for assessment of a patient's state and making a prognosis of a traumatic disease. This study is devoted to semiautomated segmentation of DAI lesions on T2*-weighted brain magnetic resonance (MR) images. A radiologist outlines the regions containing lesions, and the lesions are further automatically delineated inside these regions. A proposed algorithm for automated segmentation of DAI lesions inside specified regions is based on contouring algorithm which treats the image as a 3D topological map where a pixel's intensity corresponds to its height. It builds isolines of an intensity function. Lesion contours are among these isolines. In order to distinguish true lesion contours from other closed contours obtained by contouring algorithm machine learning approach is exploited. A labeled training base with positive (lesions) and negative (non-lesions or lesion parts) examples of closed contours is used to train the classifier. The algorithm was evaluated with real T2*-weighted brain MRI images.

关键词： Magnetic resonance

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Understanding System Characteristics of Online Erasure Coding on Scalable, Distributed and Large-Scale SSD Array systems

arXiv

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arXiv 2017年

作者： Koh, Sungjoon Zhang, Jie Kwon, Miryeong Yoon, Jungyeon Donofrio, David Kim, Namsung Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory School of Integrated Technology Yonsei University Lawrence Berkeley National Laboratory Sk Telecom University of Illinois Urbana-Champaign

Large-scale systems with arrays of solid state disks (SSDs) have become increasingly common in many computing segments. To make such systems resilient, we can adopt erasure coding such as Reed-Solomon (RS) code as an alternative to replication because erasure coding can offer a significantly lower storage cost than replication. To understand the impact of using erasure coding on system performance and other system aspects such as CPU utilization and network traffic, we build a storage cluster consisting of approximately one hundred processor cores with more than fifty high-performance SSDs, and evaluate the cluster with a popular open-source distributed parallel file system, Ceph. Then we analyze behaviors of systems adopting erasure coding from the following five viewpoints, compared with those of systems using replication: (1) storage system I/O performance;(2) computing and software overheads;(3) I/O amplification;(4) network traffic among storage nodes;(5) the impact of physical data layout on performance of RS-coded SSD arrays. For all these analyses, we examine two representative RS configurations, which are used by Google and Facebook file systems, and compare them with triple replication that a typical parallel file system employs as a default fault tolerance mechanism. Lastly, we collect 54 block-level traces from the cluster and make them available for other researchers. Copyright © 2017, The Authors. All rights reserved.

关键词： File organization

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Particle swarm and population structure 18

Particle swarm and population structure

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2018 Genetic and Evolutionary Computation Conference, GECCO 2018

作者： Fernandes, Carlos M. Rosa, Agostinho C. Fachada, Nuno Laredo, J.L.J. Merelo, J.J. LARSyS: Laboratory for Robotics and Systems in Engineering and Science University of Lisbon Portugal HEI-LAB - Digital Human-Environment and Interactions Labs Universidade Lusófona Lisbon Portugal LITIS University of Le Havre Le Havre France Department of Computer Architecture University of Granada Granada Spain

ISBN: (纸本)9781450357647

We investigate the convergence speed, accuracy, robustness and scalability of PSOs structured by regular and random graphs with 3 ≤ k ≤ n. The main conclusion is that regular and random graphs with the same averaged connectivity may result in significantly different performance, namely when is low. © 2018 Copyright is held by the owner/author(s).

关键词： Particle swarm optimization (PSO)

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Impact of virtual execution environments on processor energy consumption and hardware adaptation 06

Impact of virtual execution environments on processor energy...

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VEE 2006 - 2nd International Conference on Virtual Execution Environments

作者： Hu, Shiwen John, Lizy K. Networking and Computing Systems Group Freescale Semiconductor Inc. 7700 W. Parmer Lane Austin TX 78729 United States Laboratory for Computer Architecture University of Texas at Austin 1 University Station C0803 Austin TX 78712 United States

ISBN: (纸本)9781595933324

During recent years, microprocessor energy consumption has been surging and efforts to reduce power and energy have received a lot of attention. At the same time, virtual execution environments (VEEs), such as Java virtual machines, have grown in popularity. Hence, it is important to evaluate the impact of virtual execution environments on microprocessor energy consumption. This paper characterizes the energy and power impact of two important components of VEEs, Just-in-time (JIT) optimization and garbage collection. We find that by reducing instruction counts, JIT optimization significantly reduces energy consumption, while garbage collection incurs runtime overhead that consumes more energy. Importantly, both JIT optimization and garbage collection decrease the average power dissipated by a program. Detailed analysis reveals that both JIT optimizer and JIT optimized code dissipate less power than un-optimized code. On the other hand, being memory bound and with low ILP, the garbage collector dissipates less power than the application code, but rarely affects the average power of the latter. Adaptive microarchitectures are another recent trend for energy reduction where microarchitectural resources can be dynamically tuned to match program runtime requirements. This research reveals that both JIT optimization and garbage collection alter a program's behavior and runtime requirements, which considerably affects the adaptation of configurable hardware units, and influences the overall energy consumption. This work also demonstrates that the adaptation preferences of the two VEE services differ substantially from those of the application code. Both VEE services prefer a simple core for high energy reduction. On the other hand, the JIT optimizer usually requires larger data caches, while the garbage collector rarely benefits from large data caches. The insights gained in this paper point to novel techniques that can further reduce microprocessor energy consumption. Cop

关键词： Virtual reality

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Introduction of system level architecture exploration using the SpecC methodology

Introduction of system level architecture exploration using ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： L. Cai D. Gajski M. Olivarez Department of Information and Computer Science University of California Irvine Irvine CA USA Motorola Architecture and Systems Laboratory Austin TX USA

ISBN: (纸本)0780366859

To implement chip design on satisfactory target architectures, architecture exploration should be done at higher levels of abstraction, in the earliest design stages. Using the SpecC language, an executable system level design language, system level architecture exploration can proceed easily and smoothly as the system specification is being created. A SpecC methodology of system level architecture exploration is introduced within this paper to illustrate this process. The design of a JPEG encoder is used as an example to illustrate the system level architecture exploration methodology.

关键词： computer architecture System-level design Process design Specification languages Design methodology Transform coding computer science Chip scale packaging Time to market System testing

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