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Practical Stabilization of Passive Nonlinear systems with Limited Control

IFAC-PapersOnLine 2019年第16期52卷 460-465页

作者： B. Jayawardhana M.Z. Almuzakki A. Tanwani Engineering and Technology Institute Groningen Faculty of Science and Engineering University of Groningen The Netherlands Department of Computer Science Faculty of Science and Computer Universitas Pertamina Jakarta Indonesia Laboratory for Analyses and Architecture of Systems (LAAS) –CNRS Université de Toulouse France

This article addresses output feedback stabilization of continuous-time nonlinear systems by choosing control actions from a finite set. Working under the assumption that the system under consideration is passive and large-time norm observable, we propose a static feedback mapping, from the output space to the finite set of control actions, which is shown to be practically stabilizing if the convex hull of certain control actions (in the chosen finite set) contains the origin in its interior. Consequently, to construct this stabilizing feedback, it suffices to have, in addition to a zero symbol, another m + 1 elements in the control set which form an m -simplex in ℝ m (the input, and output space).

关键词： Nonlinear passive systems finite control set output feedback binary control

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MemoryIO: An Extended I/O Technology in Embedded systems

MemoryIO: An Extended I/O Technology in Embedded Systems

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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China

MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.

关键词： Embedded system Payloads Switches Clocks Storage area networks Physical layer Protocols

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AgilePkgC: An Agile System Idle State architecture for Energy Proportional Datacenter Servers 22

AgilePkgC: An Agile System Idle State Architecture for Energ...

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Georgia Antoniou Haris Volos Davide B. Bartolini Tom Rollet Yiannakis Sazeides Jawad Haj Yahya Computer Architecture Laboratory Department of Computer Science University of Cyprus Computing Systems Lab Huawei Zurich Research Center Rivos Inc. Mountain View California United States

ISBN: (纸本)9781665462723

Modern user-facing applications deployed in data-centers use a distributed system architecture that exacerbates the latency requirements of their constituent microservices (30--250μs). Existing CPU power-saving techniques degrade the performance of these applications due to the long transition latency (order of 100μs) to wake up from a deep CPU idle state (C-state). For this reason, server vendors recommend only enabling shallow core C-states (e.g., CC1) for idle CPU cores, thus preventing the system from entering deep package C-states (e.g., PC6) when all CPU cores are idle. This choice, however, impairs server energy proportionality since power-hungry resources (e.g., IOs, uncore, DRAM) remain active even when there is no active core to use them. As we show, it is common for all cores to be idle due to the low average utilization (e.g., 5 -- 20%) of datacenter servers running user-facing *** propose to reap this opportunity with AgilePkgC (APC), a new package C-state architecture that improves the energy proportionality of server processors running latency-critical applications. APC implements PC1A (package C1 agile), a new deep package C-state that a system can enter once all cores are in a shallow C-state (i.e., CC1) and has a nanosecond-scale transition latency. PC1A is based on four key techniques. First, a hardware-based agile power management unit (APMU) rapidly detects when all cores enter a shallow core C-state (CC1) and triggers the system-level power savings control flow. Second, an IO Standby Mode (IOSM) places IO interfaces (e.g., PCIe, DMI, UPI, DRAM) in shallow (nanosecond-scale transition latency) low-power modes. Third, a CLM Retention (CLMR) mode rapidly reduces the CLM (Cache-and-home-agent, Last-level-cache, and Mesh network-on-chip) domain's voltage to its retention level, drastically reducing its power consumption. Fourth, APC keeps all system PLLs active in PC1A to allow nanosecond-scale exit latency by avoiding PLL re-locking ove

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An Improvement on the Linear Algebraic Attack for the Indeterminate Equation Encryption Scheme

An Improvement on the Linear Algebraic Attack for the Indete...

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International Symposium on Information Theory and Its Applications, ISITA

作者： Yasuhiko Ikematsu Koichiro Akiyama Tsuyoshi Takagi Department of Mathematical Informatics The University of Tokyo Tokyo Japan Computer Architecture and Network Systems Laboratory Corporate R&D Center Toshiba Corporation

ISBN: (纸本)9781538682234;9784885523182

At SAC2017, Akiyama et al. proposed the indeterminate equation encryption scheme whose security is based on a solution problem of indeterminate equation. It is an extension of algebraic surface encryption scheme. A public key X for this scheme is a polynomial in two variables over a finite ring. Akiyama et al. also proposed two attacks, the linear algebraic attack (LAA) and the key recovery attack (KRA), by using the lattice structure associated with this scheme. In this paper, we give an improvement on LAA. Also we explain the relation between our improvement and the improvement on LAA proposed by Xagawa and examine parameters that those attacks fail by experiments. As a result, we conclude that if the total degree of the public key X is one, then KRA is more efficient than LAA and if that of X is two, then LAA is more efficient than KRA.

关键词： Encryption Lattices Public key Informatics Quantum computing

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Efficient Strategies for Workload Distribution in Heterogeneous Computing systems

Efficient Strategies for Workload Distribution in Heterogene...

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IEEE International Conference on Computational Science and Engineering Workshops (CSEWORKSHOPS)

作者： Jean Marcos Laine Edson Toshimi Midorikawa Laboratory of Architecture and High Performance Computing Department of Computer Engineering and Digital Systems Polytechnic School University of São Paulo Sao Paulo Brazil

ISBN: (纸本)9780769532578

An effective workload distribution has a prime rule on reducing the total execution time of a parallel application on heterogeneous environments, such as computational grids and heterogeneous clusters. This paper presents two approaches to workload distribution based on analytical models developed to performance prediction of parallel applications, named VRP and VRP-SS. The workload is distributed based on relative performance ratios, obtained by analytical models constructed according to the rules described in the PEMPIs methodology. In the experimental tests we evaluated the strategies and compared them using MPI applications. The results showed the efficiency of our strategies by reducing the total execution time and improving the workload balance.

关键词： Load management Analytical models Indexes Processor scheduling Computational modeling Ethernet networks SDRAM

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Design of NIC Based on I/O Processor for Cluster Interconnect Network

Design of NIC Based on I/O Processor for Cluster Interconnec...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Dongdong Wu Ninghui Sun National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

An effective interconnect network interface card (NIC) is critical to the achievement of a high-performance cluster system. An original NIC architecture based on the Intel IOP310 I/O processor chipset is presented in this paper. The NIC is a part of DCNet, which is the cluster interconnect network developed by NCIC. The I/O processor makes it powerful for the NIC to offload the processing of communication protocol from the host CPU. In the NIC architecture, the memory bus is extended to be a local bus for system peripheral interconnection, and a memory integrated network interface (MINI) is implemented and embedded. The testing results of DCNet show that the NIC obtains reasonable user-level communication performance, and prove that the NIC architecture, which based on I/O processor and the MINI approach, is feasible and effective to achieve the high performance.

关键词： computer architecture computer networks Network interfaces Supercomputers Bandwidth Intelligent systems Intelligent networks computer interfaces Power system interconnection Protocols

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FPGA-based architecture of 3-D HWT using distributed arithmetic (DA)

FPGA-based architecture of 3-D HWT using distributed arithme...

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IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES)

作者： Azlan Muharam Afandi Ahmad VLSI Architecture and Systems Design Research Laboratory Universiti Tun Hussein Onn Malaysia (UTHM) Beg Berkunci Johor Department of Computer Engineering UTHM

This paper describes the design and implementation of three-dimensional (3-D) Haar with transpose-based computation and distributed arithmetic (DA). As a results of the separately property of the multi-dimensional Haar wavelet transform (HWT), the proposed architecture has been implemented using a cascade of three N-point one-dimensional (1-D) Haar and two transpose memories for a 3-D volume of N × N × N, suitable for 3-D medical image compression. The 3-D HWT architecture were implemented on SubRIO-9632 board National Instrument. Experimental result and analysis of area, power consumption and maximum frequency are discussed in this paper.

关键词： Field programmable gate arrays Biomedical imaging Image coding Table lookup Discrete wavelet transforms

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Superconducting processors for HTMT: issues and challenges

Superconducting processors for HTMT: issues and challenges

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Frontiers of Massively Parallel Computation

作者： K.B. Theobald G.R. Gao T.L. Sterling Computer Architecture and Parallel Systems Laboratory Department of Electrical and Computer Engineering University of Delaware Newark DE USA NASA Jet Propulsion Laboratory /Center for Advanced Computing Research California Institute of Technology Pasadena CA USA

The Hybrid Technology Multi-Threading project is a long-term study of the feasibility of combining several emerging technologies to reach 1 petaFLOPS within ten years. HTMT will combine high-speed superconductor processors, semiconductor memories with built-in processors, high-speed optical interconnects, and high-density holographic storage. While there are major challenges in all aspects of this project, those in processor architecture are the focus of this paper. Fundamental differences between RSFQ circuits and conventional semiconductor circuits, including a radical jump in clock speed, make today's processor design approaches inappropriate for HTMT. Sequential instruction dispatching, even within the lowest programming unit (a strand), will lead to unacceptably high latencies, hence poor performance. We propose alternative processor designs which use fine-grain synchronizations between individual instructions in order to avoid these bottlenecks.

关键词： Random access memory Optical buffering Holography Holographic optical components Delay computer architecture Optical interconnections Electrical capacitance tomography Quantum computing Clocks

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Low-cost on-line fault detection using control flow assertions

Low-cost on-line fault detection using control flow assertio...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Rajesh Venkatasubramanian J.P. Hayes B.T. Murray Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Brighton Technical Center Delphi Automotive Systems Brighton MI UK

A control flow fault occurs when a processor fetches and executes an incorrect next instruction. Executable assertions, i.e., special instructions that check some invariant properties of a program, provide a powerful and low-cost method for on-line detection of hardware-induced control flow faults. We propose a technique called ACFC (Assertions for Control Flow Checking) that assigns an execution parity to a basic block, and uses the parity bit to detect faults. Using a graph model of a program, we classify control flow faults into skip, re-execute and multi-path faults. We derive some necessary conditions for these faults to manifest themselves as execution parity errors. To force a control flow fault to excite a parity error, the target program is instrumented with additional instructions. Special assertions are inserted to detect such parity errors. We have a developed a preprocessor that takes a C program as input and inserts ACFC assertions automatically. We have implemented a software-based fault injection tool SFIG which takes advantage of the GNU debugger. Fault injection experiments show that ACFC incurs less performance overhead (around 47%) and memory overhead (around 30%) than previous techniques, with no significant loss in fault coverage.

关键词： Fault detection computer architecture Laboratories Automotive engineering Rivers Testing Costs Registers Instruments Performance loss

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Stability of Linear systems under Extended Weakly-Hard Constraints

arXiv

引用

arXiv 2021年

作者： Vreman, Nils Pazzaglia, Paolo Magron, Victor Wang, Jie Maggio, Martina The Department of Automatic Control Lund University Sweden The Department of Computer Science Saarland University Germany The Laboratory for Analysis and Architecture of Systems CNRS France The Academy of Mathematics and Systems Science CAS China

Control systems can show robustness to many events, like disturbances and model inaccuracies. It is natural to speculate that they are also robust to sporadic deadline misses when implemented as digital tasks on an embedded platform. This paper proposes a comprehensive stability analysis for control systems subject to deadline misses, leveraging a new formulation to describe the patterns experienced by the control task under different handling strategies. Such analysis brings the assessment of control systems robustness to computational problems one step closer to the controller implementation. Copyright © 2021, The Authors. All rights reserved.

关键词： Networked control systems

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