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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Jorge Gonz'lez-Domínguez Osni A. Marques María J. Martín Guillermo L. Taboada Juan Touriño Universidade da Coruna A Coruna Galicia ES Computational Research Division Lawrence Berkeley National Laboratory CA USA Computer Architecture Group Department of Electronics and Systems University of A Coruña Spain

Partitioned Global Address Space (PGAS) languages offer programmers a shared memory view that increases their productivity and allow locality exploitation to obtain good performance on current large-scale distributed memory systems. UPCBLAS is a parallel numerical library for dense matrix computations using the PGAS Unified Parallel C (UPC) language. The interface of this library exploits the characteristics of the PGAS memory model and thus it is easier to use than MPI-based libraries. This paper addresses the implementation of solvers of systems of equations through Cholesky and LU factorizations in UPC using UPCBLAS. The developed codes are experimentally evaluated and compared to the MPI versions using ScaLAPACK. Parallel solvers of equations are present in many parallel numerical applications and they have been traditionally developed in MPI. This work shows that UPCBLAS can be considered as a good alternative to the MPI-based libraries for increasing the productivity of numerical application developers.

关键词： Libraries Message systems Instruction sets Electronics packaging Equations Vectors Arrays

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A New Algorithm for Non-rigid Point Matching Using Geodesic Graph Model

A New Algorithm for Non-rigid Point Matching Using Geodesic ...

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IEEE International Conference on Mechatronics and Automation

作者： Deheng Qian Tianshi Chen Hong Qiao State Key Laboratory of Management and Control for Complex Systems Institute of Automation Chinese Academy of Sciences Beijing 100190 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9781479970995

Point matching is a problem of finding the optimum matching between two sets of key points which are extracted from the surfaces of objects. A popular approach represents the features of a set of points with a graph model. Traditionally, the measurement applied in the graph model is the Euclidian distance, which is not suitable for objects with non-rigid deformations. In this paper, we propose a novel graph model called the geodesic graph model (GGM) which uses a geodesic-like distance as its measurement. GGM can better tackle non-rigid deformations because the geodesic-like distance is a kind of invariant structural feature during non-rigid deformations. The building process of the GGM is justified under the assumption that all the key points are spanning on a manifold. To further handle the deviations of key point locations, we come up with a feature weighting process to increase our algorithm's robustness. We conduct several experiments on different kinds of deformations over several widely used datasets. Experimental results demonstrate the effectiveness of our algorithm.

关键词： Point matching non-rigid deformation manifold geodesic distance

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Effects of multithreading on data and workload distribution for distributed-memory multiprocessors

Effects of multithreading on data and workload distribution ...

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International Symposium on Parallel Processing

作者： A. Sohn M. Sato Namhoon Yoo J.-L. Gaudiot Computer and Information Science Department New Jersey Institute of Technology Newark NJ USA Computer Architecture Section Electro Technical Laboratory Tsukuba Ibaraki Japan Department of EE-Systems University of Southern California Los Angeles CA USA

While data and workload distribution can be tailored to fit a particular problem to a particular distributed-memory architecture, it is often difficult to do so for various practical issues. This paper presents our study on multithreading for distributed-memory multiprocessors. Specifically, we investigate the effects of multithreading on data distribution and workload distribution with variable thread granularity. Various types of workload distribution strategies are defined along thread granularity. Three types of data distribution strategies are investigated: row-wise cyclic, k-way partial-row cyclic and blocked distribution. We have implemented all of these on the 80-processor EM-4 distributed-memory multiprocessor using highly-sequential Gaussian elimination with partial pivoting and highly-parallel matrix multiplication. Experimental results indicated that multithreading can offset the loss that is due to the mismatch of data distribution to workload distribution for even sequential and irregular problems while giving high absolute performance.

关键词： Multithreading Yarn Distribution strategy Performance loss

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AgileWatts: An Energy-Efficient CPU Core Idle-State architecture for Latency-Sensitive Server Applications 22

AgileWatts: An Energy-Efficient CPU Core Idle-State Architec...

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Jawad Haj Yahya Haris Volos Davide B. Bartolini Georgia Antoniou Jeremie S. Kim Zhe Wang Kleovoulos Kalaitzidis Tom Rollet Zhirui Chen Ye Geng Onur Mutlu Yiannakis Sazeides Rivos Inc Mountain View California United States Computer Architecture Laboratory Department of Computer Science University of Cyprus Computing Systems Lab Huawei Zurich Research Center Department of Information Technology and Electrical Engineering ETH Zurich Switzerland

ISBN: (纸本)9781665462723

User-facing applications running in modern datacenters exhibit irregular request patterns and are implemented using a multitude of services with tight latency requirements (30--250μs). These characteristics render existing energy-conserving techniques ineffective when processors are idle due to the long transition time (order of 100μs) from a deep CPU core idle power state (C-state). While prior works propose management techniques to mitigate this inefficiency, we tackle it at its root with AgileWatts (AW): a new deep CPU core C-state architecture optimized for datacenter server processors targeting latency-sensitive *** drastically reduces the transition latency from deep CPU core idle power states while retaining most of their power savings based on three key ideas. First, AW eliminates the latency (several microseconds) of saving/restoring the core context when powering-off/-on the core in a deep idle state by i) implementing medium-grained power-gates, carefully distributed across the CPU core, and ii) retaining context in the power-ungated domain. Second, AW eliminates the flush latency (several tens of microseconds) of the L1/L2 caches when entering a deep idle state by keeping L1/L2 content power-ungated. A small control logic also remains ungated to serve cache coherence traffic. AW implements cache sleep-mode and leakage reduction for the power-ungated domain by lowering a core's voltage to the minimum operational level. Third, using a state-of-the-art power efficient all-digital phase-locked loop (ADPLL) clock generator, AW keeps the PLL active and locked during the idle state, cutting microseconds of wake-up latency at negligible power *** evaluation with an accurate industrial-grade simulator calibrated against an Intel Skylake server shows that AW reduces the energy consumption of Memcached by up to 71% (35% on average) with <1% end-to-end performance degradation. We observe similar trends for other evaluated services (MySQL and Kafka).

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Exploring Fault-Tolerant Erasure Codes for Scalable All-Flash Array Clusters

arXiv

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arXiv 2019年

作者： Koh, Sungjoon Zhang, Jie Kwon, Miryeong Yoon, Jungyeon Donofrio, David Kim, Nam Sung Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology School of Integrated Technology Yonsei Institute Convergence Technology Yonsei University Lawrence Berkeley National Laboratory Georgia Institute of Technology University of Illinois Urbana-Champaign

—Large-scale systems with all-flash arrays have become increasingly common in many computing segments. To make such systems resilient, we can adopt erasure coding such as Reed-Solomon (RS) code as an alternative to replication because erasure coding incurs a significantly lower storage overhead than replication. To understand the impact of using erasure coding on the system performance and other system aspects such as CPU utilization and network traffic, we build a storage cluster that consists of approximately 100 processor cores with more than 50 high-performance solid-state drives (SSDs), and evaluate the cluster with a popular open-source distributed parallel file system, called Ceph. Specifically, we analyze the behaviors of a system adopting erasure coding from the following five viewpoints, and compare with those of another system using replication: (1) storage system I/O performance;(2) computing and software overheads;(3) I/O amplification;(4) network traffic among storage nodes, and (5) impact of physical data layout on performance of RS-coded SSD arrays. For all these analyses, we examine two representative RS configurations, used by Google file systems, and compare them with triple replication employed by a typical parallel file system as a default fault tolerance mechanism. Lastly, we collect 96 block-level traces from the cluster and release them to the public domain for the use of other researchers. Copyright © 2019, The Authors. All rights reserved.

关键词： File organization

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Parallel-in-Time Multi-Level Integration of the Shallow-Water Equations on the Rotating Sphere

arXiv

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arXiv 2019年

作者： Hamon, François P. Schreiber, Martin Minion, Michael L. Center for Computational Sciences and Engineering Lawrence Berkeley National Laboratory Berkeley United States Chair of Computer Architecture and Parallel Systems Technical University of Munich Germany Department of Applied Mathematics Lawrence Berkeley National Laboratory Berkeley United States

The modeling of atmospheric processes in the context of weather and climate simulations is an important and computationally expensive challenge. The temporal integration of the underlying PDEs requires a very large number of time steps, even when the terms accounting for the propagation of fast atmospheric waves are treated implicitly. Therefore, the use of parallel-in-time integration schemes to reduce the time-to-solution is of increasing interest, particularly in the numerical weather forecasting field. We present a multi-level parallel-in-time integration method combining the Parallel Full Approximation Scheme in Space and Time (PFASST) with a spatial discretization based on Spherical Harmonics (SH). The iterative algorithm computes multiple time steps concurrently by interweaving parallel high-order fine corrections and serial corrections performed on a coarsened problem. To do that, we design a methodology relying on the spectral basis of the SH to coarsen and interpolate the problem in space. The methods are evaluated on the shallow-water equations on the sphere using a set of tests commonly used in the atmospheric flow community. We assess the convergence of PFASST-SH upon refinement in time. We also investigate the impact of the coarsening strategy on the accuracy of the scheme, and specifically on its ability to capture the high-frequency modes accumulating in the solution. Finally, we study the computational cost of PFASST-SH to demonstrate that our scheme resolves the main features of the solution multiple times faster than the serial schemes. Copyright © 2019, The Authors. All rights reserved.

关键词： Harmonic analysis

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Synthesizing executable models of object oriented architectures

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systems Engineering 2003年第4期6卷 266-300页

作者： Wagenhals, Lee W. Haider, Sajjad Levis, Alexander H. Systems Architecture Laboratory C3I Center George Mason University Fairfax VA 22030-4444 Electrical and Computer Engineering Department School of Information Technology and Engineering GMU U.S. Air Force

The U.S. Department of Defense (DoD) has mandated the development of architectures to support the acquisition of systems that are interoperable and will meet the needs of military coalitions. This paper provides a general description of an architecting process based on object orientation and UML. It then provides a rationale for style constraints on the use of UML artifacts for representing DoD Command, Control, Communications, computers, Intelligence, Surveillance, and Reconnaissance (C4ISR) architectures. Finally the paper describes a mapping between the UML artifacts and an executable model based on colored Petri nets that can be used for logical, behavioral, and performance evaluation of the architecture. A procedure for the conversion is also provided. © 2003 Wiley Periodicals, Inc.

关键词： Object oriented programming

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Vision-based Unmanned Aerial Vehicle detection and tracking for sense and avoid systems

Vision-based Unmanned Aerial Vehicle detection and tracking ...

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IEEE/RSJ International Conference on Intelligent Robots and systems

作者： Krishna Raj Sapkota Steven Roelofsen Artem Rozantsev Vincent Lepetit Denis Gillet Pascal Fua Alcherio Martinoli Computer Vision Laboratory School of Communication and Computer Sciences école Polytechnique Fédérale de Lausanne (EPFL) Switzerland Distributed Intelligent Systems and Algorithms Laboratory School of Architecture Civil and Environmental Engineering EPFL Switzerland Institute for Computer Graphics and Vision TU Graz Austria Coordination and Interaction System Group School of Engineering EPFL Switzerland

ISBN: (纸本)9781509037636

We propose an approach for on-line detection of small Unmanned Aerial Vehicles (UAVs) and estimation of their relative positions and velocities in the 3D environment from a single moving camera in the context of sense and avoid systems. This problem is challenging both from a detection point of view, as there are no markers on the targets available, and from a tracking perspective, due to misdetection and false positives. Furthermore, the methods need to be computationally light, despite the complexity of computer vision algorithms, to be used on UAVs with limited payload. To address these issues we propose a multi-staged framework that incorporates fast object detection using an AdaBoost-based approach, coupled with an on-line visual-based tracking algorithm and a recent sensor fusion and state estimation method. Our framework allows for achieving real-time performance with accurate object detection and tracking without any need of markers and customized, high-performing hardware resources.

关键词： Target tracking Object detection Collision avoidance Cameras Visualization Detectors

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Parallelization of LU decomposition on the godson-Tv1 many-core architecture

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Jisuanji Xuebao/Chinese Journal of computers 2009年第11期32卷 2157-2167页

作者： Long, Guo-Ping Fan, Dong-Rui Key Laboratory of Computer Systems and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

The many-core architecture is increasingly becoming a promising computing platform due to the advancement of semi-conductor technology. LU decomposition is a widely used kernel in both scientific and engineering computations. Although there are a lot of related works on traditional parallel architectures, there is still little work focusing on parallelizing it on many-core architectures. This paper investigates this problem from three aspects: load balancing, latency hiding and performance modeling. There are three contributions of this work: Firstly, a novel load balancing technique has been introduced to overcome the limitations of 2D scatter decomposition. Experimental results show that the proposed scheme achieves 20% performance improvement without optimization and 40% improvement after optimization. Secondly, an analytical performance model is presented. Quantitative experimental study shows that by carefully hiding memory latency through on chip memory hierarchy and for a selected block size, the upper bound of theoretical performance can be approximated by experiments. Experimental results also reveal two primary causes which make theoretical speedup hard to achieve: limited DRAM bandwidth and resource contention of on-chip network.

关键词： Parallel architectures

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ACG-Engine: An Inference Accelerator for Content Generative Neural Networks

ACG-Engine: An Inference Accelerator for Content Generative ...

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IEEE International Conference on computer-Aided Design

作者： Haobo Xu Ying Wang Yujie Wang Jiajun Li Bosheng Liu Yinhe Han University of Chinese Academy of Sciences State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences

The technological breakthrough in Generative Adversarial Networks (GAN) has propelled the advancement of content generative applications such as AI-based paintings, style transfer, and music composition. However, in contrast to previous deep learning models for prediction and categorization, generative networks generally rely on instance normalization (IN) layer for better feature distribution, which performs significantly better than batch normalization(BN) in image style-transfer, image to image translation, etc. Unlike batch or group normalization that can be fused into convolutional layers and ignored during the network inference stage, an instance normalization layer induces intensive computation and memory access. However, prior deep learning accelerator designs for traditional Neural Network and Generative Adversarial Networks mostly focus on the acceleration of convolution and deconvolution layer but lack of support for IN operations, which could become a performance bottleneck on edge devices with insufficient computational power. To address this problem, we propose an inference accelerator for content generation (ACG-Engine) aimed to support the fundamental operations of generative networks, including convolution layers, deconvolution layers, specifically instance normalization layer. We performed a hardware-aware mathematical transformation of the IN operation for less computation complexity and memory-friendliness, so that it can be efficiently mapped to the classic 2D processing element array. Owing to the proposed optimization techniques, ACG-Engine achieves 4.56X speedup and improve power efficiency up to 29X compared to prior baseline acceleration scheme in generative network acceleration. In addition, ACG-Engine can achieve performance comparable to the classic CNN-specific accelerators with negligible power consumption and area overhead.

关键词： Performance evaluation Deep learning Deconvolution Convolution Neural networks Generative adversarial networks Acceleration

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