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18th USENIX Conference on File and Storage Technologies, FAST 2020

作者： Zhang, Jie Kwon, Miryeong Swift, Michael Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory University of Wisconsin at Madison

ISBN: (纸本)9781939133120

NVMe is designed to unshackle flash from a traditional storage bus by allowing hosts to employ many threads to achieve higher bandwidth. While NVMe enables users to fully exploit all levels of parallelism offered by modern SSDs, current firmware designs are not scalable and have difficulty in handling a large number of I/O requests in parallel due to its limited computation power and many hardware contentions. We propose DeepFlash, a novel manycore-based storage platform that can process more than a million I/O requests in a second (1MIOPS) while hiding long latencies imposed by its internal flash media. Inspired by a parallel data analysis system, we design the firmware based on many-to-many threading model that can be scaled horizontally. The proposed DeepFlash can extract the maximum performance of the underlying flash memory complex by concurrently executing multiple firmware components across many cores within the device. To show its extreme parallel scalability, we implement DeepFlash on a many-core prototype processor that employs dozens of lightweight cores, analyze new challenges from parallel I/O processing and address the challenges by applying concurrency-aware optimizations. Our comprehensive evaluation reveals that DeepFlash can serve around 4.5 GB/s, while minimizing the CPU demand on microbenchmarks and real server workloads. Copyright © Proc. of the 18th USENIX Conference on File and Storage Tech., FAST 2020. All rights reserved.

关键词： Firmware

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Constrained Optimization with Decision-Dependent Distributions

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IEEE Transactions on Automatic Control 2025年

作者： Wang, Zifan Liu, Changxin Parisini, Thomas Zavlanos, Michael M. Johansson, Karl H. KTH Royal Institute of Technology Division of Decision and Control Systems School of Electrical Engineering and Computer Science Sweden Digital Futures StockholmSE-10044 Sweden East China University of Science and Technology Key Laboratory of Smart Manufacturing in Energy Chemical Process Ministry of Education Shanghai200237 China Imperial College London Department of Electrical and Electronic Engineering LondonSW7 2AZ United Kingdom Aalborg University Department of Electronic Systems Denmark University of Trieste Department of Engineering and Architecture Italy Duke University Department of Mechanical Engineering and Materials Science DurhamNC United States

In this paper we deal with stochastic optimization problems where the data distributions change in response to the decision variables. Traditionally, the study of optimization problems with decision-dependent distributions has assumed either the absence of constraints or fixed constraints. This work considers a more general setting where the constraints can also dynamically adjust in response to changes in the decision variables. Specifically, we consider linear constraints and analyze the effect of decision-dependent distributions in both the objective function and constraints. Firstly, we establish a sufficient condition for the existence of a constrained equilibrium point, at which the distributions remain invariant under retraining. Moreover, we propose and analyze two algorithms: repeated constrained optimization and repeated dual ascent. For each algorithm, we provide sufficient conditions for convergence to the constrained equilibrium point. Furthermore, we explore the relationship between the equilibrium point and the optimal point for the constrained decision-dependent optimization problem. Notably, our results encompass previous findings as special cases when the constraints remain fixed. To show the effectiveness of our theoretical analysis, we provide numerical experiments on both a market problem and a dynamic pricing problem for parking based on real-world data. © 1963-2012 IEEE.

关键词： Optimization algorithms

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Government open systems interconnection: Profile in progress

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Library Hi Tech 1990年第4期8卷 111-118页

作者： Mills, Kevin L. Systems and Network Architecture Division National Computer Systems Laboratory National Institute of Standards and Technology United States

The emergence of Open systems Interconnection protocols, as specified within the U.S. Government Open systems Interconnection Profile (GOSIP) Federal Information Processing Standard (FTPS), provides both an opportunity for, and a means of achieving, interoperability within multi-vendor networks. The GOSIP can easily benefit inexperienced users, yet provides the flexibility to serve more sophisticated users. The standard mandates specifications that will be met by a multitude of vendor products, with initial offerings already available. While meeting a useful set of initial networking needs, the FIPS will evolve to include new applications, improvements to the initial applications, new network technologies, and major new functions. GOSIP will permit government agencies to gain better control over their computer network procurements, accruing greater and greater cost savings as the number of government computer networks increases. © 1990, MCB UP Limited

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Exploring system challenges of ultra-low latency solid state drives 10

Exploring system challenges of ultra-low latency solid state...

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10th USENIX Workshop on Hot Topics in Storage and File systems, HotStorage 2018, co-located with USENIX ATC 2018

作者： Koh, Sungjoon Lee, Changrim Kwon, Miryeong Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory Yonsei University Korea Republic of

We quantitatively characterize performance behaviors of a real ultra-low latency (ULL) SSD archive by using a real 800GB Z-SSD prototype, and analyze system-level challenges that the current storage stack exhibits. Specifically, our comprehensive empirical evaluations and studies demonstrate i) diverse performance analyses of the ULL SSD, including a wide range of latency and queue examinations, ii) I/O interference characteristics, which are considered as one of the great performance bottlenecks of modern SSDs, and iii) efficiency and challenge analyses of a polling-based I/O service (newly added into Linux 4.4 kernel) by comparing it with conventional interrupt-based I/O services. In addition to these performance characterizations, we discuss several system implications, which are required to take a full benefit of ULL SSD in the future. © USENIX Workshop on Hot Topics in Storage and File systems, HotStorage 2018, co-located with USENIX ATC *** right reserved.

关键词： File organization

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Design and implementation of communication system of the Dawning 6000 supercomputer

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中国计算机科学前沿 2010年第4期4卷 466-474页

作者： Qiang LI Bo LI Zhigang HUO Ninghui SUN National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China

An increasing number of supercomputers adopt a heterogeneous architecture, consisting of both general purpose CPUs and specialized accelerators. Such design is beneficial for scalability and power, but on the other hand, heterogeneity brings new challenges in communication systems to connect heterogeneous components and provide support for programming. The communication system of the Dawning 6000 connectstwo kinds of heterogeneous processors, Loongson and AMD, and adopts a three layer architecture with an intranode layer between heterogeneous components. To efficiently connect heterogeneous components, the system forms a global address space and provides a mechanism for message transmission via an in-node global store; and employing Infiniband network, provides an OS-bypassing virtualization method to share an Infiniband card between nodes. To facilitate programming on heterogeneous processors, it supports unified parallel C (UPC), with a modified complier based on global address space. Also, aspecial collective network is implemented for collective operations. Results obtained from a prototype system prove these features to be both feasible and efficient.

关键词： hyper parallel processing (HPP) global address space (GAS) virtualization Dawning 6000 unified parallel C (UPC)

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What’s Missing in Agile Hardware Design? Verification!

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Journal of computer Science & Technology 2023年第4期38卷 735-736页

作者： Babak Falsafi Parallel Systems Architecture Laboratory Institute of Computer and Communication SciencesSchool of Computer andCommunication SciencesEcole Polytechnique Fédérale de LausanneLausanneCH-1015Switzerland

Agile hardware design is an approach to developing hardware systems that draws inspiration from the principles and practices of agile software *** emphasizes collaboration,flexibility,iterative development,and quick adaptation to changing *** agile hardware design,the focus is on delivering functionalhardware systems in shorter development cycles while maintaining high-quality and customer *** particular,agile hardware design is of great interest in the open-source hardware ***-sourcehardware development—such as RISC-V—is at the forefront of initiatives to democratize hardware and drive innovation in chip design *** design is instrumental for the RISC-V community because it supportsrapid iteration,accommodates the evolving RISC-V standard and the addition of custom extensions,improvescommunity collaboration and time-to-market,and addresses the design challenges associated with complex architectural features.

关键词： hardware agile architectural

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Coping with very high latencies in petaflop computer systems 2nd

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2nd International Symposium on High Performance Computing, ISHPC 1999

作者： Ryan, Sean Amaral, José N. Gao, Guang Ruiz, Zachary Marquez, Andres Theobald, Kevin Computer Architecture and Parallel Systems Laboratory University of Delaware NewarkDE United States

ISBN: (纸本)3540659692

The very long and highly variable latencies in the deep memory hierarchy of a petaflop-scale architecture design, such as the Hybrid Technology Multi-Threaded architecture (HTMT) [13], present a new challenge to its programming and execution model. A solution to coping with such high and variable latencies is to directly and explicitly expose the different memory regions of the machine to the program execution model, allowing better management of communication. In this paper we describe the novel percolation model that lies at the heart of the HTMT program execution model [13]. The Percolation Model combines multithreading with dynamic prefetching of coarse-grain contexts. In the past, prefetching techniques have concentrated on moving blocks of data within the memory hierarchy. Instead of only moving contiguous blocks of data, the thread percolation approach manages contexts that include data, program instructions, and control states. The main contributions of this paper include the specification of the HTMT runtime execution model based on the concept of percolation, and a discussion of the role of the compiler in a machine that exposes the memory hierarchy to the programming model. © 1999, Springer-Verlag. All rights reserved.

关键词： Solvents

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Dependency-aware unequal erasure protection codes

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Journal of Zhejiang University-Science A(Applied Physics & Engineering) 2006年第z1期7卷 27-33页

作者： BOUABDALLAH Amine LACAN Jérme Laboratory for Analysis and Architecture of Systems Toulouse 31077 France Applied Mathematics and Computer Science DepartmentENSICAToulouse 31056France Telecommunications for Space and AeronauticToulouse 31000France

Classical unequal erasure protection schemes split data to be protected into classes which are encoded independently. The unequal protection scheme presented in this paper is based on an erasure code which encodes all the data together according to the existing dependencies. A simple algorithm generates dynamically the generator matrix of the erasure code according to the packets streams structure, i.e., the dependencies between the packets, and the rate of the code. This proposed erasure code was applied to a packetized MPEG4 stream transmitted over a packet erasure channel and compared with other classical protection schemes in terms of PSNR and MOS. It is shown that the proposed code allows keeping a high video quality-level in a larger packet loss rate range than the other protection schemes.

关键词： Data dependencies integration Unequal erasure protection (UEP) Lossy networks Reliable video transmissions MPEG4 video codec

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Implementation of neural network-based nonlinear adaptive model predictive control over a service-oriented computer network

Implementation of neural network-based nonlinear adaptive mo...

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作者： Akpan, Vincent A. Samaras, Ioakeim K. Hassapis, George D. Department of Electrical and Computer Engineering Laboratory of Computer Systems Architecture Aristotle University of Thessaloniki 54124 Thessaloniki Greece

ISBN: (纸本)9781424474264

This paper presents a new neural network-based nonlinear adaptive model predictive control algorithm and its implementation over a service-oriented computer network. The computer network is based on the device profile for web services. At each sampling instant, the algorithm identifies a nonlinear process model using a recurrent neural network. On the basis of the identified model, the nonlinear adaptive model predictive control is updated and the control actions are applied. The network training is performed with data obtained from the prior plant operation under different input disturbances. The proposed nonlinear model identification and nonlinear adaptive model predictive control were applied to the temperature control of a fluidized bed furnace reactor and tested by simulating the reactor operation on the proposed service-oriented computer network. Input step changes and long range output prediction results show good predictive and adaptive control performance. The computation time of the proposed algorithms running on the proposed network architecture was less than the sampling period of the process with a bounded round trip delay. These simulation results indicate that the proposed identification and control algorithms can be of practical use to processes with similar dynamics with the fluidized bed reactor. This is because their realization over a service-oriented computer network which may be the physical platform of their implementation does not introduce delays of such a level that may alter the required sampling time for good control performance. © 2010 AACC.

关键词： Chemical reactors

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Way sharing set associative cache architecture

Way sharing set associative cache architecture

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25th International Conference on VLSI Design, VLSID 2012 and the 11th International Conference on Embedded systems

作者： Janraj, C.J. Kalyan, T. Venkata Warrier, Tripti Mutyam, Madhu Computer Architecture and Systems Laboratory Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai 600036 India

ISBN: (纸本)9780769546384

In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit nonuniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty. © 2012 IEEE.

关键词： Energy conservation

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