检索结果-内蒙古大学图书馆

IEEE Conference on Wireless Communications and Networking

作者： Yu Gu Baohua Zhao Yusheng Ji Jie Li Information Systems Architecture Science Research Division National Institute of Information Tokyo Japan State Key Laboratory of Networking and Switching Technology Beijing China Department of Computer Science Tsukuba Science City University of Tsukuba Ibaraki Japan

We address the optimal sink scheduling problem in wireless sensor networks (WSNs). The problem is inherently difficult since sink scheduling and data routing are tightly coupled. Previous approaches either have questionable performance due to no joint considerations, or are based on relaxed constraints. Our aim is to fill in this blank in the research. First, by discretizing continuous time, we develop a novel bound technique to connect time-varying routes with the placement of sinks. This bounding technique transforms time-related constraints into pattern-based ones and allows us to mathematically formulate this optimization in a pattern-based way. The complexity of directly solving this optimization is intractable; therefore, on the basis of column generation (CG), a computationally efficient algorithm is developed to reduce the complexity by decomposing the problem into sub-problems and iteratively solving them to approach optimality. Simulations demonstrate the efficiency of the algorithm and substantiate the importance of sink mobility in energy-constrained sensor networks.

关键词： Wireless sensor networks Optimization Relays Routing Processor scheduling Complexity theory USA Councils

来源：评论

学校读者我要写书评

暂无评论

Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

引用

Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization Program processors Adders Delay

来源：评论

学校读者我要写书评

暂无评论

Design and implementation of communication system of the Dawning 6000 supercomputer

引用

中国计算机科学前沿 2010年第4期4卷 466-474页

作者： Qiang LI Bo LI Zhigang HUO Ninghui SUN National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China National Research Center for Intelligent Computing Systems Beijing 100190China Key Laboratory of Computer System and Architecture Chinese Academy of SciencesBeijing 100190China

An increasing number of supercomputers adopt a heterogeneous architecture, consisting of both general purpose CPUs and specialized accelerators. Such design is beneficial for scalability and power, but on the other hand, heterogeneity brings new challenges in communication systems to connect heterogeneous components and provide support for programming. The communication system of the Dawning 6000 connectstwo kinds of heterogeneous processors, Loongson and AMD, and adopts a three layer architecture with an intranode layer between heterogeneous components. To efficiently connect heterogeneous components, the system forms a global address space and provides a mechanism for message transmission via an in-node global store; and employing Infiniband network, provides an OS-bypassing virtualization method to share an Infiniband card between nodes. To facilitate programming on heterogeneous processors, it supports unified parallel C (UPC), with a modified complier based on global address space. Also, aspecial collective network is implemented for collective operations. Results obtained from a prototype system prove these features to be both feasible and efficient.

关键词： hyper parallel processing (HPP) global address space (GAS) virtualization Dawning 6000 unified parallel C (UPC)

来源：评论

学校读者我要写书评

暂无评论

Theoretical Treatment of Sink Scheduling Problem in Wireless Sensor Networks

Theoretical Treatment of Sink Scheduling Problem in Wireless...

引用

IEEE Conference on computer Communications Workshops

作者： Yu Gu Yusheng Ji Jie Li Baohua Zhao Information Systems Architecture Science Research Division National Institute of Informatics Department of Computer Science University of Tsukuba State Key Laboratory of Networking and Switching Technology

ISBN: (纸本)9781457702495

Sink Scheduling, in the form of scheduling multiple sinks among sink sites to leverage traffic burden, is an effective mechanism for the energy-efficiency of wireless sensor networks (WSNs). Due to the inherent difficulty (NP-hard in general), existing works on this topic mainly focus on heuristic/greedy algorithms and theoretic results remain unknown. In this paper, we fill in the research blank with two algorithms. The first one is based on the Column Generation (CG). It decomposes the original problem into two sub problems and solve them iteratively to approach the optimal solution. However, due to its high computational complexity, this algorithm is only suitable for small scale networks. The other one is a polynomial-time algorithm based on relaxation techniques to obtain an upperbound, which can serve as a performance benchmark for other algorithms on this problem. Through comprehensive simulations, we evaluate the efficiency of proposed algorithms.

关键词： Wireless sensor networks Performance metrics Sinks Relaxation Techniques Energy efficiency original problem algorithms

来源：评论

学校读者我要写书评

暂无评论

Implementation of neural network-based nonlinear adaptive model predictive control over a service-oriented computer network

Implementation of neural network-based nonlinear adaptive mo...

引用

作者： Akpan, Vincent A. Samaras, Ioakeim K. Hassapis, George D. Department of Electrical and Computer Engineering Laboratory of Computer Systems Architecture Aristotle University of Thessaloniki 54124 Thessaloniki Greece

ISBN: (纸本)9781424474264

This paper presents a new neural network-based nonlinear adaptive model predictive control algorithm and its implementation over a service-oriented computer network. The computer network is based on the device profile for web services. At each sampling instant, the algorithm identifies a nonlinear process model using a recurrent neural network. On the basis of the identified model, the nonlinear adaptive model predictive control is updated and the control actions are applied. The network training is performed with data obtained from the prior plant operation under different input disturbances. The proposed nonlinear model identification and nonlinear adaptive model predictive control were applied to the temperature control of a fluidized bed furnace reactor and tested by simulating the reactor operation on the proposed service-oriented computer network. Input step changes and long range output prediction results show good predictive and adaptive control performance. The computation time of the proposed algorithms running on the proposed network architecture was less than the sampling period of the process with a bounded round trip delay. These simulation results indicate that the proposed identification and control algorithms can be of practical use to processes with similar dynamics with the fluidized bed reactor. This is because their realization over a service-oriented computer network which may be the physical platform of their implementation does not introduce delays of such a level that may alter the required sampling time for good control performance. © 2010 AACC.

关键词： Chemical reactors

来源：评论

学校读者我要写书评

暂无评论

A hierarchical approach for the fabrication of three-dimensional microbattery electrodes

A hierarchical approach for the fabrication of three-dimensi...

引用

International Solid-State Sensors, Actuators and Microsystems Conference

作者： Gerasopoulos, K. Pomerantseva, E. McCarthy, M. Culver, J. Wang, C. Ghodssi, R. MEMS Sensors and Actuators Laboratory Drexel University College Park MD United States Department of Materials Science and Engineering Drexel University College Park MD United States Institute for Systems Research Drexel University College Park MD United States Department of Electrical and Computer Engineering Drexel University College Park MD United States Department of Plant Sciences and Landscape Architecture Drexel University College Park MD United States Department of Chemical and Biomolecular Engineering Drexel University College Park MD United States Department of Mechanical Engineering and Mechanics Drexel University College Park MD United States University of Maryland College Park MD United States Drexel University Philadelphia PA United States

ISBN: (纸本)9781457701573

The first successful demonstration of virus-structured, hierarchical electrodes for three-dimensional (3-D) Li-ion microbattery architectures is reported in this paper. The electrodes consist of electroplated gold micropillars and virus-structured nanocomposite materials with a TiO2 anode layer deposited on a nickel-coated viral template. Micropatterning increases the active electrode surface area and electrochemical characterization results verify an improvement in microbattery capacity by up to a factor of four compared to nanostructures alone. © 2011 IEEE.

关键词： Viruses

来源：评论

学校读者我要写书评

暂无评论

Implementation of Neural Network-Based Nonlinear Adaptive Model Predictive Control over a Service-Oriented computer Network

Implementation of Neural Network-Based Nonlinear Adaptive Mo...

引用

American Control Conference

作者： Vincent A. Akpan Ioakeim K. Samaras George D. Hassapis Laboratory of Computer Systems Architecture Department of Electrical and Computer Engineering Aristotle University of Thessaloniki 54124 Thessaloniki Greece

ISBN: (纸本)9781424474264

关键词： computer network Adaptive Model device profile control performance Predictive control Temperature control procedural model Simulation results control action REACTOR OPERATION recurrent neural nets sampling time Fluidized bed reactors

来源：评论

学校读者我要写书评

暂无评论

Building a personal high performance computer with heterogeneous processors

Building a personal high performance computer with heterogen...

引用

International Conference on Grid and Cloud Computing

作者： Li, Qiang Huo, Zhigang Sun, Ninghui National Research Center for Intelligent Computing Systems Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769543130

Personal high performance computer (PHPC) requires lower cost and high performance. The Teraflops PHPC systems with special accelerator units like GPGPU have been presented, but they have difficulties in programming, compatibility and applicability. In this paper, we present HPP-PHPC, a hybrid architecture of heterogeneous processors connected by non-coherent off-chip system bus. The performance of HPP-PHPC is ensured by special processors integrated with vector units and high-efficiency interconnection between heterogeneous processors. And by the adoption of general processors and features like global physical address space and synchronization semantics in hardware, HPP-PHPC is more compatible and convenient for massage passing and PGAS programming model. Also it is more applicable to most applications, including those with many execution branches. Initial results obtained from our prototype system have proved our design. © 2010 IEEE.

关键词： Semantics

来源：评论

学校读者我要写书评

暂无评论

Evaluation of runtime task mapping heuristics with rSesame - a case study 10

Evaluation of runtime task mapping heuristics with rSesame -...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Kamana Sigdel Mark Thompson Carlo Galuzzi Andy D. Pimentel Koen Bertels Computer Engineering Laboratory EEMCS Delft University of Technnology Netherlands Computer Systems Architecture Group University of Amsterdam Netherlands

ISBN: (纸本)9783981080162

rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we want to evaluate the framework's characteristics by showing that it can easily and quickly model, simulate and compare a wide range of runtime mapping heuristics from various domains. A case study with a Motion-JPEG (MJPEG) application demonstrates that the presented model can be efficiently used to model and simulate a wide variety of mapping heuristics as well as to perform runtime exploration of various non-functional design parameters such as execution time, number of reconfigurations, area usage, etc.

关键词： Runtime Reconfigurable architectures Partitioning algorithms Streaming media Design engineering Laboratories computer architecture Computational modeling computer simulation Processor scheduling

来源：评论

学校读者我要写书评

暂无评论

Virtualizing modern high-speed interconnection networks with performance and scalability

Virtualizing modern high-speed interconnection networks with...

引用

作者： Li, Bo Huo, Zhigang Zhang, Panyong Meng, Dan National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542201

As one of the most important enabling technologies of cloud computing, virtualization brings to HPC good manageability, online system maintenance, performance isolation and fault isolation. Furthermore, previous study on VMM-bypass I/O that virtualizes OS-bypass networks (e.g. Infini- Band) relieved the worry of performance degradation coming along with virtualization. In this paper, we address the scalability challenges imposed upon OS-bypass networks under virtualized environments. The eXtended Reliable Connection (XRC) transport, proposed in modern high-speed interconnection networks to address the scalability problem in large scale applications, would not work in virtualized environments. To solve the problem, we propose VM-proof XRC design to eliminate the scalability gap between virtualized and native environments. Prototype evaluation shows that the virtualization of modern high-speed interconnection networks could get the same raw performance and scalability as in native non-virtualized environment with our VM-proof XRC design. The connection memory scalability shows a potential of 16 times improvement on virtualized clusters composed of 16-core nodes. © 2010 IEEE.

关键词： Scalability

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：