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Pacific Rim International Symposium on Dependable Computing

作者： Brian T. Gold Babak Falsafi James C. Hoe Computer Architecture Laboratory Carnegie Mellon University USA Sun MicroSystems Laboratories Inc. Menlo Park CA USA Parallel Systems Architecture Laboratory École Polytechnique Fédérale de Lausanne Switzerland

Distributed shared-memory (DSM) multiprocessors provide a scalable hardware platform, but lack the necessary redundancy for mainframe-level reliability and availability. Chip-level redundancy in a DSM server faces a key challenge: the increased latency to check results among redundant components. To address performance overheads, we propose a checking filter that reduces the number of checking operations impeding the critical path of execution. Furthermore, we propose to decouple checking operations from the coherence protocol, which simplifies the implementation and permits reuse of existing coherence controller hardware. Our simulation results of commercial workloads indicate average performance overhead is within 4% (9% maximum) of tightly coupled DMR solutions.

关键词： Hardware Redundancy Filters Protocols Protection computer architecture Delay Clocks Circuit faults Availability

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Dynamic thermal management in 3D multicore architectures 09

Dynamic thermal management in 3D multicore architectures

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ayse K. Coskun Jose L. Ayala David Atienza Tajana Simunic Rosing Yusuf Leblebici Computer Science and Engineering Department (CSE) University of California San Diego USA Computer Architecture and Automation Department (DACYA) Complutense University of Madrid Spain Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne Switzerland Microelectronics Systems Laboratory (LSM) EPF Lausanne Switzerland

ISBN: (纸本)9783981080155

Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architectures is a recently proposed approach to overcome the power consumption and delay problems associated with the interconnects by reducing the length of the wires going across the chip. However, 3D integration introduces serious thermal challenges due to the high power density resulting from placing computational units on top of each other. In this work, we first investigate how the existing thermal management, power management and job scheduling policies affect the thermal behavior in 3D chips. We then propose a dynamic thermally-aware job scheduling technique for 3D systems to reduce the thermal problems at very low performance cost. Our approach can also be integrated with power management policies to reduce energy consumption while avoiding the thermal hot spots and large temperature variations.

关键词： Thermal management Multicore processing Energy management Power system management Energy consumption Processor scheduling Transistors computer architecture Delay Wires

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A massively parallel hardware architecture for ray-tracing

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International Journal of High Performance systems architecture 2009年第1期2卷 26-34页

作者： Nery, A.S. Nedjah, N. França, F.M.G. Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE P.O. Box 68511 21941-972 Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Rua Sao Francisco Xavier 524 Sala 5145-F Maracana 20.550-900 Rio de Janeiro RJ Brazil Universidade Federal do Rio de Janeiro Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering State University of Rio de Janeiro Brazil Brazil

Real time performance of non-interactive rendering of three-dimensional scenes is usually unachievable. Ray tracing is one of the methods used for rendering such scenes. The performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. In contrast, many parallel implementations of ray tracing have been enabling real time performance, as the underlying algorithm can be massively parallelised. Thus, it is expected that a custom parallel design in hardware is likely to achieve the acceptable performance standards. In this paper, we propose a hardware architecture, which we call GridRT, capable of dealing with the main desirable features of ray tracing, such as shadows and reflections effects, imposing low requirements in terms of silicon area while achieving acceptable performance in terms of rendering time. This architecture achieves is efficient yet compact as it explores the massive parallelism offered by the intrinsic structure of the algorithm. The design exploits the usage the spatial data structure of regular grids. Copyright © 2009 Inderscience Enterprises Ltd.

关键词： Ray tracing

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Parallelization of LU decomposition on the godson-Tv1 many-core architecture

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Jisuanji Xuebao/Chinese Journal of computers 2009年第11期32卷 2157-2167页

作者： Long, Guo-Ping Fan, Dong-Rui Key Laboratory of Computer Systems and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

The many-core architecture is increasingly becoming a promising computing platform due to the advancement of semi-conductor technology. LU decomposition is a widely used kernel in both scientific and engineering computations. Although there are a lot of related works on traditional parallel architectures, there is still little work focusing on parallelizing it on many-core architectures. This paper investigates this problem from three aspects: load balancing, latency hiding and performance modeling. There are three contributions of this work: Firstly, a novel load balancing technique has been introduced to overcome the limitations of 2D scatter decomposition. Experimental results show that the proposed scheme achieves 20% performance improvement without optimization and 40% improvement after optimization. Secondly, an analytical performance model is presented. Quantitative experimental study shows that by carefully hiding memory latency through on chip memory hierarchy and for a selected block size, the upper bound of theoretical performance can be approximated by experiments. Experimental results also reveal two primary causes which make theoretical speedup hard to achieve: limited DRAM bandwidth and resource contention of on-chip network.

关键词： Parallel architectures

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Modeling and dynamic management of 3D multicore systems with liquid cooling

Modeling and dynamic management of 3D multicore systems with...

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IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Ayse K. Coskun José L. Ayala David Atienza Tajana Simunic Rosing Computer Science and Engineering Department (CSE) University of California San Diego USA Computer Architecture and Automation Department (DACYA) Complutense University of Madrid Spain Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne (EPFL) Switzerland

Three-dimensional (3D) circuits reduce communication delay in multicore SoCs, and enable efficient integration of cores, memories, sensors, and RF devices. However, vertical integration of layers exacerbates the reliability and thermal problems, and cooling efficiency becomes a limiting factor. Liquid cooling is a solution to overcome the accelerated thermal problems imposed by multi-layer architectures. In this paper, we first provide a 3D thermal simulation model including liquid cooling, supporting both fixed and variable fluid injection rates. Our model has been integrated in HotSpot to study the impact on multicore SoCs. We design and evaluate several dynamic management policies that complement liquid cooling. Our results for 3D multicore SoCs, which are based on 3D versions of UltraSPARC T1, show that thermal management approaches that combine liquid cooling with proactive task allocation are extremely effective in preventing temperature problems. Our proactive management technique provides an additional 75% average reduction in hot spots in comparison to applying only liquid cooling. Furthermore, for systems capable of varying the coolant flow rate at runtime, our feedback controller increases the improvement to 95% on average.

关键词： Three dimensional displays Liquid cooling Thermal management Microchannel Through-silicon vias Thermal resistance

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Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips

Comparison of fault-tolerance techniques for massively defec...

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International Conference on Mixed Design of Integrated Circuits and systems (MIXDES)

作者： Jacques Henri Collet Mihalis Psarakis Piotr Zajac Dimitris Gizopoulos Andrzej Napieralski Laboratoire d'Analyse et d'Architecture des Systèmes du CNRS Université de Toulouse Toulouse France Computer Systems Laboratory Department of Informatics University of Piraeus Piraeus Greece Department of Microelectronics and Computer Science Technical University of Lodz Lodz Poland

The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimensions, the increase of atomic fluctuations and the massive occurrence of physical defects. We focus on fault tolerance at the architectural level, and especially on fault-tolerance approaches, which are based on chip self-diagnosis and self-reconfiguration. We study test and reconfiguration methodologies in massively defective nanoscale devices, either at fine granularity field programmable devices or at coarse granularity multi-core arrays. In particular, we address the important question of up to which point could future chips have self-organizing fault-tolerance mechanisms to autonomously ensure their own dependable operation. In the case of FPGAs, we present known fault tolerant approaches and discuss their limitations in future nanoscale devices. In the case of multicore arrays, we show that such properties as self-diagnosis, self-isolation of faulty elements and self-reorganization of communication routes are possible.

关键词： Fault tolerance Circuit testing Circuit faults Redundancy Protection Field programmable gate arrays CMOS technology Phased arrays Multicore processing Nanoscale devices

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HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs

HPP-Controller: An intra-node controller designed for connec...

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IEEE International Conference on Cluster Computing

作者： Qiang Li Panyong Zhang Ninghui Sun Chinese Academy and Sciences China Chinese Academy of Sciences Beijing Beijing CN National Research Center of Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences China

Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial results show that HPP-Controller has low latency of 0.75 us and high bandwidth close to bandwith of HT links.

关键词： Joining processes Central Processing Unit Delay Bandwidth Supercomputers Petascale computing Control systems Field programmable gate arrays Access protocols Sun

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Analysis and Design of Mobile Model for DTN

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电子学报(英文版) 2009年第4期

作者： LIN Zhiting LIN Zhiting QU Yugui QU Yugui JI Yusheng JI Yusheng ZHAO Baohua ZHAO Baohua Department of Computer Science University of Science and Technology of China Hefei 230027 China Department of Computer Science University of Science and Technology of China Hefei 230027 China Province Key Laboratory of Software in Computing and Communication Hcfei 230027 China Province Key Laboratory of Software in Computing and Communication Hcfei 230027 China Information Systems Architecture Science Research Division National Institute of Info~natics Tokyo Japan) Information Systems Architecture Science Research Division National Institute of Info~natics Tokyo Japan)

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MemoryIO: An Extended I/O Technology in Embedded systems

MemoryIO: An Extended I/O Technology in Embedded Systems

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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China

MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.

关键词： Embedded system Payloads Switches Clocks Storage area networks Physical layer Protocols

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Efficient Strategies for Workload Distribution in Heterogeneous Computing systems

Efficient Strategies for Workload Distribution in Heterogene...

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IEEE International Conference on Computational Science and Engineering Workshops (CSEWORKSHOPS)

作者： Jean Marcos Laine Edson Toshimi Midorikawa Laboratory of Architecture and High Performance Computing Department of Computer Engineering and Digital Systems Polytechnic School University of São Paulo Sao Paulo Brazil

ISBN: (纸本)9780769532578

An effective workload distribution has a prime rule on reducing the total execution time of a parallel application on heterogeneous environments, such as computational grids and heterogeneous clusters. This paper presents two approaches to workload distribution based on analytical models developed to performance prediction of parallel applications, named VRP and VRP-SS. The workload is distributed based on relative performance ratios, obtained by analytical models constructed according to the rules described in the PEMPIs methodology. In the experimental tests we evaluated the strategies and compared them using MPI applications. The results showed the efficiency of our strategies by reducing the total execution time and improving the workload balance.

关键词： Load management Analytical models Indexes Processor scheduling Computational modeling Ethernet networks SDRAM

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