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International Conference on CAD systems in Microelectronics (CADSM)

作者： W. Cichalewski A. Napieralski H. Camon B. Estibals Department of Microelectronics and Computer Science TUL Lodz Poland Laboratory for Analysis and Architecture of Systems CNRS Toulouse France

This paper is devoted to the study of the static and dynamical behaviour of a ID torsion single crystal silicon micro-mirror. The aim is to create a parametric model of such mirror allowing to use a simple calculation program to avoid expensive and long FEM simulations. This study tries to put in place a modelling to define the best structure with regard to various specification by taking into account the technological possibilities and to simulate the experimental characteristics before the expensive technological process.

关键词： Analytical models Mathematical model Micromechanical devices MATLAB Mirrors Electrodes Torque Silicon Electrostatics Voltage

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Automatic instruction set extension and utilization for embedded processors

Automatic instruction set extension and utilization for embe...

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International Conference on Application Specific systems (ASAP), architectures and Processors

作者： A. Peymandoust L. Pozzi P. Ienne G. De Micheli Computer Systems Laboratory University of Stanford Stanford CA USA Processor Architecture Laboratory Swiss Federal Institute of Technology Lausanne Switzerland

There is a growing demand for application-specific embedded processors in system-on-a-chip designs. Current tools and design methodologies often require designers to manually specialize the processor based on an application. Moreover, the use of the new complex instructions added to the processor is often left to designers' ingenuity. We present a solution that automatically groups dataflow operations in the application software as potential new complex instructions. The set of possible instructions is then automatically used for code generation combined with high-level arithmetic optimizations using symbolic algebra. Symbolic arithmetic manipulations provide a novel and effective method for instruction selection that is necessary due to the complexity of the automatically identified instructions. We have used our methodology to automatically add new instructions to Tensilica processors for a set of examples. Our results show that our tools improve designers productivity and efficiently specialize an embedded processor for the given application such that the execution time is greatly improved.

关键词： Application specific processors Application software Design methodology Time to market Laboratories computer architecture Arithmetic Algebra Costs Embedded system

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Organizational architectures and mission requirements: A model to determine congruence

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systems Engineering 2003年第3期6卷 184-194页

作者： Handley, Holly A.H. Levis, Alexander H. Systems Architectures Laboratory C3I Center George Mason University Fairfax VA 22030 George Mason University Systems Architecture Laboratory Department of Electrical Computer and Systems Engineering C3I Center System Architectures Laboratory

In order to determine congruence between proposed organizational architectures and evolving mission requirements, an executable model was developed in support of a subject experiment testing the hypothesis that an organization congruent with an expected mission results in better performance than a noncongruent organization. The model is based on the task process, the sequence of stages that occur in order to complete a task, where the delays of each stage are based on the interactions of the task with decision-makers and resources;in this case, tasks are limited to simple tasks completed by a single decision-maker with a single resource. The model is configured to a particular organizational design and simulated with a scenario, a list of tasks and their parameters that characterize the mission. Congruence is determined by using regression analysis to fit a linear equation to the output of the simulation and computing the coefficient of determination to evaluate the fit. The model was developed with trial experiment data and validated with post-experimental results. This model provides the foundation for a future, second order model that will include multiple decision-makers interacting with multiple resources to complete complex tasks. © 2003 Wiley Periodicals, Inc.

关键词： Architectural design

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Low-cost on-line fault detection using control flow assertions

Low-cost on-line fault detection using control flow assertio...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Rajesh Venkatasubramanian J.P. Hayes B.T. Murray Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI USA Brighton Technical Center Delphi Automotive Systems Brighton MI UK

A control flow fault occurs when a processor fetches and executes an incorrect next instruction. Executable assertions, i.e., special instructions that check some invariant properties of a program, provide a powerful and low-cost method for on-line detection of hardware-induced control flow faults. We propose a technique called ACFC (Assertions for Control Flow Checking) that assigns an execution parity to a basic block, and uses the parity bit to detect faults. Using a graph model of a program, we classify control flow faults into skip, re-execute and multi-path faults. We derive some necessary conditions for these faults to manifest themselves as execution parity errors. To force a control flow fault to excite a parity error, the target program is instrumented with additional instructions. Special assertions are inserted to detect such parity errors. We have a developed a preprocessor that takes a C program as input and inserts ACFC assertions automatically. We have implemented a software-based fault injection tool SFIG which takes advantage of the GNU debugger. Fault injection experiments show that ACFC incurs less performance overhead (around 47%) and memory overhead (around 30%) than previous techniques, with no significant loss in fault coverage.

关键词： Fault detection computer architecture Laboratories Automotive engineering Rivers Testing Costs Registers Instruments Performance loss

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Synthesizing executable models of object oriented architectures

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systems Engineering 2003年第4期6卷 266-300页

作者： Wagenhals, Lee W. Haider, Sajjad Levis, Alexander H. Systems Architecture Laboratory C3I Center George Mason University Fairfax VA 22030-4444 Electrical and Computer Engineering Department School of Information Technology and Engineering GMU U.S. Air Force

The U.S. Department of Defense (DoD) has mandated the development of architectures to support the acquisition of systems that are interoperable and will meet the needs of military coalitions. This paper provides a general description of an architecting process based on object orientation and UML. It then provides a rationale for style constraints on the use of UML artifacts for representing DoD Command, Control, Communications, computers, Intelligence, Surveillance, and Reconnaissance (C4ISR) architectures. Finally the paper describes a mapping between the UML artifacts and an executable model based on colored Petri nets that can be used for logical, behavioral, and performance evaluation of the architecture. A procedure for the conversion is also provided. © 2003 Wiley Periodicals, Inc.

关键词： Object oriented programming

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An adaptive low-power transmission scheme for on-chip networks

An adaptive low-power transmission scheme for on-chip networ...

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15th International Symposium on System Synthesis

作者： Worm, Frédéric Thiran, Patrick Ienne, Paolo De Micheli, Giovanni Processor Architecture Laboratory EPFL Lausanne Switzerland Lab. for Computer Communications EPFL Lausanne Switzerland Computer Systems Laboratory Stanford University Stanford CA United States

systems-on-Chip (SoC) are evolving toward complex heterogeneous multiprocessors made of many predesigned macrocells or subsystems with application-specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme;it minimises the interconnect voltage swing and frequency subject to workload requirements and S/N conditions. Simulation results show that tangible savings in energy can be attained while achieving at the same time more robustness to large variations in actual workload, noise, and technology quality (all quantities easily mispredicted in very complex systems and advanced technologies). It can be argued that traditional worst-case correct-by-design paradigm will be less and less applicable in future multibillion transistor SoC and deep sub-micron technologies;this work represents a first example towards robust adaptive designs.

关键词： Microprocessor chips

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Human systems integration and advanced technology in engineering department workload and manpower reduction

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NAVAL ENGINEERS JOURNAL 2003年第1期115卷 57-65页

作者： Lively, KA Seman, AJ Kirkpatrick, M KENNETH A. LIVELY graduated from the University of Colorado with a BS in applied mathematics and an MS in mathematics in 1976 and from the Massachusetts Institute of Technology with an MS in electrical engineering and the degree ocean engineer in naval architecture and marine engineering in 1984. He retired from the U.S. Navy in 1989 after 23 years of service. Assignments included electrical officer on the USS Constellation (CV 64) project engineer for the DDG 51 machinery control system (NAVSEA) and DDG 51 Technical Director (NAVSEA). He was vice president of the PDI Division of Bird-Johnson Company from July 1989 to November 1998 where he managed various gas turbine and machinery controls related development projects. He joined Anteon Corporation's Systems Engineering Group as senior controls engineer in December 1998 where he provided technical support to the integrated power systems program (NAVSEA PMS 510) and managed the Office of Naval Research Afloat Laboratory. DR. MARK KIRKPATRICK is currently an independent consultant in human factors and work-load/manning analysis and modeling. He holds a Ph.D. degree in experimental psychology from The Ohio State University and has 34 years of experience in applied human factors. From 1982 through 2000 Dr. Kirkpatrick served as the senior vice president of Carlow International. Prior to joining Carlow in 1982 Dr. Kirkpatrick served as a member of the technical staff at North American Rockwell's Missiles Division and as a project director and vice president for Essex Corporation. His areas of expertise include workload simulation task analysis operator-in-the-loop simulation human performance experimentation statistical analysis and human factors T&E. He has directed and/or participated in human factors projects for the U.S. Navy U.S. Army NASA Department of Transportation the U.S. Nuclear Regulatory Commission and private industry. ANTHONY J. SEMAN III is the technical manager for the reduced ship's crew by virtual presence (RSVP) advanced technology d

Aboard current ships, such as the DDG 51, engineering control and damage control activities are manpower intensive. It is anticipated that, for future combatants, the workload demand arising from operation of systems under conditions of normal steaming and during casualty response will need to be markedly reduced via automated monitoring, autonomous control, and other technology initiatives. Current DDG 51 class ships can be considered as a manpower baseline and under Condition III typical engineering control involves seven to eight watchstanders at manned stations in the Central Control Station, the engine rooms and other machinery spaces. In contrast to this manning level, initiatives such as DD 21 and the integrated engineering plant (IEP) envision a partnership between the operator and the automation system, with more and more of the operator's functions being shifted to the automation system as manning levels decrease. This paper describes some human systems integration studies of workload demand reduction and, consequently, manning reduction that can be achieved due to application of several advanced technology concepts. Advanced system concept studies in relation to workload demand are described and reviewed including. Piecemeal applications of diverse automation and remote control technology concepts to selected high driver tasks in current DDG 51 activities. Development of the reduced ship's crew by virtual presence system that will provide automated monitoring and display to operators of machinery health, compartment conditions, and personnel health. The IEP envisions the machinery control system as a provider of resources that are used by various consumers around the ship. Resource needs and consumer priorities are at all times dependent upon the ship's current mission and the availability of equipment pawnbrokers.

关键词： Naval warfare

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Towards energy-aware software-based fault tolerance in real-time systems

Towards energy-aware software-based fault tolerance in real-...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： O.S. Unsal I. Koren C.M. Krishna Architecture and Real-Time Systems Laboratory Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

Many real-time systems employed in defense, space, and consumer applications have power constraints and high reliability requirements. In this paper, we focus on the relationship between fault tolerance techniques and energy consumption. In particular, we establish the energy efficiency of Application Level Fault Tolerance (ALFT) over other software-based fault tolerance methods. We then develop sensible energy-aware heuristics for ALFT schemes. The heuristics yield up to 40% energy savings.

关键词： Fault tolerant systems Real time systems Fault tolerance Redundancy Application software Power system reliability Permission Scheduling computer architecture Laboratories

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An adaptive low-power transmission scheme for on-chip networks

An adaptive low-power transmission scheme for on-chip networ...

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International Symposium on System Synthesis

作者： F. Worm P. Ienne P. Thiran G. de micheli Processor Architecture Laboratory EPF Lausanne Lausanne Switzerland Archit. Lab. Ecole Polytech. Fed. de Lausanne Switzerland Laboratory for Computer Communications and Appl EPF Lausanne Lausanne Switzerland Computer Systems Laboratory University of Stanford CA USA

systems-on- Chip (SoC) are evolving toward complex heterogeneous multiprocessors made of many predesigned macrocells or subsystems with application-specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme; it minimises the interconnect voltage swing and frequency subject to workload requirements and S/N conditions. Simulation results show that tangible savings in energy can be attained while achieving at the same time more robustness to large variations in actual workload, noise, and technology quality (all quantities easily mispredicted in very complex systems and advanced technologies). It can be argued that traditional worst-case correct-by-design paradigm will be less and less applicable in future multibillion transistor SoC and deep sub-micron technologies; this work represents a first example towards robust adaptive designs.

关键词： Network-on-a-chip Crosstalk Signal design Voltage Circuit noise Magnetic noise Encoding Noise reduction Noise robustness Integrated circuit interconnections

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A study of memory system performance of multimedia applications 01

A study of memory system performance of multimedia applicati...

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Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems

作者： Sohum Sohoni Rui Min Zhiyong Xu Yiming Hu Operating Systems and Computer Architecture Laboratory Department of Electrical & Computer Engineering and Computer Science P.O. Box 210030 University of Cincinnati Cincinnati OH

ISBN: (纸本)9781581133349

Multimedia applications are fast becoming one of the dominating workloads for modern computer systems. Since these applications normally have large data sets and little data-reuse, many researchers believe that they have poor memory behavior compared to traditional programs, and that current cache architectures cannot handle them well. It is therefore important to quantitatively characterize the memory behavior of these applications in order to provide insights for future design and research of memory systems. However, very few results on this topic have been published. This paper presents a comprehensive research on the memory requirements of a group of programs that are representative of multimedia applications. These programs include a subset of the popular MediaBench suite and several large multimedia programs running on the Linux, Windows NT and Tru UNIX operating systems. We performed extensive measurement and trace-driven simulation experiments. We then compared the memory utilization of these programs to that of SPECint95 applications. We found that multimedia applications actually have better memory behavior than SPECint95 programs. The high cache hit rates of multimedia applications can be contributed to the following three factors. Most multimedia applications apply block partitioning algorithms to the input data, and work on small blocks of data that easily fit into the cache. Secondly, within these blocks, there is significant data reuse as well as spatial locality. The third reason is that a large number of references generated by multimedia applications are to their internal data structures, which are relatively small and can also easily fit into reasonably-sized caches.

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