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4th International Workshop on Network on Chip architectures, NoCArc 2011, in Conjunction with the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO44

作者： Jose, John Shankar, J. Shiva Mahathi, K.V. Kumar, Damarla Kranthi Mutyam, Madhu Computer Architecture and Systems Laboratory Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai-36 India

ISBN: (纸本)9781450309479

If the route computation operation in an adaptive router returns more than one output channels, the selection strategy chooses one from them based on the congestion metric used. The effectiveness of a selection strategy depends on what metric is used to identify congestion and how precisely that metric captures the actual congestion. The number of cycles a flit stays in a router is a direct indication of the contention level of the output port it desires to move out. We propose buffer Occupancy Factor based Adaptive Router (BOFAR), wherein the history of cycles spent by flits in buffers is used as the congestion metric. BOFAR outperforms the baseline architectures built on minimal odd-even adaptive router model with conventional selection strategies like count of free downstream virtual channels at reachable neighbors, and fluidity of buffers in downstream neighbors. Our experiments on 4x4 mesh NoC with various synthetic traffic patterns show that BOFAR exceeds the performance of best baseline adaptive router with 21% average and 78% maximum latency reduction at saturation load. The reduced average packet latency, increased buffer fluidity fairness, and increased saturation point of BOFAR with minimal overhead in area, power, and wiring makes it a promising alternative to existing adaptive routers in mesh NoCs. © 2011 ACM.

关键词： Network-on-chip

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Massively parallel breadth first search using a tree-structured memory model

Massively parallel breadth first search using a tree-structu...

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2012 International Workshop on Programming Models and Applications for Multicores and Manycores, PMAM 2012

作者： St. John, Tom Dennis, Jack B. Gao, Guang R. Computer Architecture and Parallel Systems Laboratory University of Delaware United States Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology United States

ISBN: (纸本)9781450312110

Analysis of massive graphs has emerged as an important area for massively parallel computation. In this paper, it is shown how the Fresh Breeze trees-of-chunks memory model may be used to perform breadth-first search of large undirected graphs. Overall, the computation can be expressed as a data flow process wherein a set of vertices to be searched is partitioned into a set of sub-domains and processed independently by many concurrent tasks. The main contributions of the paper are listed below. • We present the first case study demonstrating the power of the Fresh Breeze program execution model (PXM) in the exploitation of fine-grain parallelism found in irregular applications such as graph algorithms. • We present a novel parallel breadth-first search algorithm which is fully determinate. • We describe a unique sparse vector representation that represents the set of adjacencies for each vertex. • We provide an experimental study and analysis of our implementation. An estimate is also made of the performance that might be achieved with a massively parallel system built according to Fresh Breeze principles. © 2012 ACM.

关键词： Forestry

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Theoretical Treatment of Target Coverage in Wireless Sensor Networks

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Journal of computer Science & Technology 2011年第1期26卷 117-129页

作者：谷雨赵保华计宇生李颉 School of Computer Science University of Science and Technology of China State Key Laboratory of Networking and Switching Technology Information Systems Architecture Science Research Division National Institute of InformaticsTokyoJapan Department of Computer Science University of TsukubaTsukuba Science CityIbarakiJapan

The target coverage is an important yet challenging problem in wireless sensor networks, especially when both coverage and energy constraints should be taken into account. Due to its nonlinear nature, previous studies of this problem have mainly focused on heuristic algorithms; the theoretical bound remains unknown. Moreover, the most popular method used in the previous literature, i.e., discretization of continuous time, has yet to be justified. This paper fills in these gaps with two theoretical results. The first one is a formal justification for the method. We use a simple example to illustrate the procedure of transforming a solution in time domain into a corresponding solution in the pattern domain with the same network lifetime and obtain two key observations. After that, we formally prove these two observations and use them as the basis to justify the method. The second result is an algorithm that can guarantee the network lifetime to be at least （1 - ε） of the optimal network lifetime, where ε can be made arbitrarily small depending on the required precision. The algorithm is based on the column generation （CG） theory, which decomposes the original problem into two sub-problems and iteratively solves them in a way that approaches the optimal solution. Moreover, we developed several constructive approaches to further optimize the algorithm. Numerical results verify the efficiency of our CG-based algorithm.

关键词： target coverage wireless sensor networks time-dependent solution pattern-based solution column generation

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An adaptive low-power transmission scheme for on-chip networks

An adaptive low-power transmission scheme for on-chip networ...

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15th International Symposium on System Synthesis

作者： Worm, Frédéric Thiran, Patrick Ienne, Paolo De Micheli, Giovanni Processor Architecture Laboratory EPFL Lausanne Switzerland Lab. for Computer Communications EPFL Lausanne Switzerland Computer Systems Laboratory Stanford University Stanford CA United States

systems-on-Chip (SoC) are evolving toward complex heterogeneous multiprocessors made of many predesigned macrocells or subsystems with application-specific interconnections. Intra-chip interconnects are thus becoming one of the central elements of SoC design and pose conflicting goals in terms of low energy per transmitted bit, guaranteed signal integrity, and ease of design. This work introduces and shows first results on a novel interconnect system which uses low-swing signalling, error detection codes, and a retransmission scheme;it minimises the interconnect voltage swing and frequency subject to workload requirements and S/N conditions. Simulation results show that tangible savings in energy can be attained while achieving at the same time more robustness to large variations in actual workload, noise, and technology quality (all quantities easily mispredicted in very complex systems and advanced technologies). It can be argued that traditional worst-case correct-by-design paradigm will be less and less applicable in future multibillion transistor SoC and deep sub-micron technologies;this work represents a first example towards robust adaptive designs.

关键词： Microprocessor chips

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DC-store: eliminating noisy neighbor containers using deterministic I/O performance and resource isolation 20

DC-store: eliminating noisy neighbor containers using determ...

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Proceedings of the 18th USENIX Conference on File and Storage Technologies

作者： Miryeong Kwon Donghyun Gouk Changrim Lee Byounggeun Kim Jooyoung Hwang Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology Computer Architecture and Memory Systems Laboratory Samsung

ISBN: (纸本)9781939133120

We propose DC-store, a storage framework that offers deterministic I/O performance for a multi-container execution environment. DC-store's hardware-level design implements multiple NVM sets on a shared storage pool, each providing a deterministic SSD access time by removing internal resource conflicts. In parallel, software support of DC-Store is aware of the NVM sets and enlightens Linux kernel to isolate noisy neighbor containers, performing page frame reclaiming, from peers. We prototype both hardware and software counterparts of DC-Store and evaluate them in a real system. The evaluation results demonstrate that containerized data-intensive applications on DC-Store exhibit 31% shorter average execution time, on average, compared to those on a baseline system.

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Faster than flash: An in-depth study of system challenges for emerging ultra-low latency SSDs

arXiv

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arXiv 2019年

作者： Koh, Sungjoon Jang, Junhyeok Lee, Changrim Kwon, Miryeong Zhang, Jie Jung, Myoungsoo Computer Architecture and Memory Systems Laboratory KAIST

Emerging storage systems with new flash exhibit ultra-low latency (ULL) that can address performance disparities between DRAM and conventional solid state drives (SSDs) in the memory hierarchy. Considering the advanced low-latency characteristics, different types of I/O completion methods (polling/hybrid) and storage stack architecture (SPDK) are proposed. While these new techniques are expected to take costly software interventions off the critical path in ULL-applied systems, unfortunately no study exists to quantitatively analyze system-level characteristics and challenges of combining such newly-introduced techniques with real ULL SSDs. In this work, we comprehensively perform empirical evaluations with 800GB ULL SSD prototypes and characterize ULL behaviors by considering a wide range of I/O path parameters, such as different queues and access patterns. We then analyze the efficiencies and challenges of the polled-mode and hybrid polling I/O completion methods (added into Linux kernels 4.4 and 4.10, respectively) and compare them with the efficiencies of a conventional interrupt-based I/O path. In addition, we revisit the common expectations of SPDK by examining all the system resources and parameters. Finally, we demonstrate the challenges of ULL SSDs in a real SPDK-enabled server-client system. Based on the performance behaviors that this study uncovers, we also discuss several system implications, which are required to take a full advantage of ULL SSD in the future. Copyright © 2019, The Authors. All rights reserved.

关键词： Dynamic random access storage

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TREBIVETM: A TREe Based Integrity Verification Environment for Non-volatile Memory System 21

TREBIVETM: A TREe Based Integrity Verification Environment f...

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21st IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2015

作者： Hashimoto, Mikio Yamada, Naoko Kanai, Jun Computer Architecture and Security Systems Laboratory Corporate Research and Development Center Toshiba Corporation 1 Komukai-Toshiba-cho Saiwai-ku Kawasaki Japan

ISBN: (纸本)9781467393768

In view of the introduction of computer technologies into social infrastructure, computer security is rapidly emerging as a major real-world problem. Since control devices are left in physically insecure fields, the risk of physical attack is a greater concern than in the case of data center systems. In addition, non-volatile main memory technology may extend the threat because an attacker can easily manipulate and retrieve data stored in the memory. Much research has been done with a view to realizing secure processors with integrity tree verification, but no secure processor product with MMU capability has been commercialized so far. In this paper, TREBIVE, a TREe-Based Integrity Verification Environment, is proposed. It offers VMM-based memory integrity and confidentiality protection for existing COTS processors. A prototype VMM is constructed using ARM Cortex-A15 processors and quantitative analysis is performed using the Linux environment. The result shows a considerable amount of overhead, which is a concern. However, the results of experiments on SQLite queries support the view that the proposed method offers quicker response than whole DB image verification on existing systems. A target system model to mitigate the overhead is also proposed, in order to support robust disconnected operation of field devices. © 2015 IEEE.

关键词： computer operating systems

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Design and performance issues of cholesky and LU solvers using UPCBLAS

Design and performance issues of cholesky and LU solvers usi...

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2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

作者： González-Domínguez, Jorge Marques, Osni A. Martín, María J. Taboada, Guillermo L. Touriño, Juan Computer Architecture Group Department of Electronics and Systems University of a Coruña Spain Computational Research Division Lawrence Berkeley National Laboratory CA United States

ISBN: (纸本)9780769547015

Partitioned Global Address Space (PGAS) languages offer programmers a shared memory view that increases their productivity and allow locality exploitation to obtain good performance on current large-scale distributed memory systems. UPCBLAS is a parallel numerical library for dense matrix computations using the PGAS Unified Parallel C (UPC) language. The interface of this library exploits the characteristics of the PGAS memory model and thus it is easier to use than MPI-based libraries. This paper addresses the implementation of solvers of systems of equations through Cholesky and LU factorizations in UPC using UPCBLAS. The developed codes are experimentally evaluated and compared to the MPI versions using ScaLAPACK. Parallel solvers of equations are present in many parallel numerical applications and they have been traditionally developed in MPI. This work shows that UPCBLAS can be considered as a good alternative to the MPI-based libraries for increasing the productivity of numerical application developers. © 2012 IEEE.

关键词： Productivity

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Sprinkler: Maximizing resource utilization in many-chip solid state disks

Sprinkler: Maximizing resource utilization in many-chip soli...

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20th IEEE International Symposium on High Performance computer architecture, HPCA 2014

作者： Jung, Myoungsoo Kandemir, Mahmut T. Department of EE University of Texas at Dallas Computer Architecture and Memory Systems Laboratory United States Department of CSE Pennsylvania State University United States

ISBN: (纸本)9781479930975

Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource utilization and achieving high performance without additional NAND flash chips. Specifically, Sprinkler relaxes parallelism dependency by scheduling I/O requests based on internal resource layout rather than the order imposed by the device-level queue. In addition, Sprinkler improves flash-level parallelism and reduces the number of transactions (i.e., improves transactionallocality) by over-committing flash memory requests to specific resources. Our extensive experimental evaluation using a cycle-accurate large-scale SSD simulation framework shows that a many-chip SSD equipped with our Sprinkler provides at least 56.6% shorter latency and 1.8 -2.2 times better throughput than the state-of-the-art SSD controllers. Further, it improves overall resource utilization by 68.8% under different I/O request patterns and provides, on average, 80.2% more flash-level parallelism by reducing half of the flash memory requests at runtime. © 2014 IEEE.

关键词： Flash memory

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Parallel scientific computing in promoter on the interface between application modelling and language design 98

Parallel scientific computing in promoter on the interface b...

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1998 ACM Symposium on Applied Computing, SAC 1998

作者： Besch, Matthias Heber, Gerd Wilhelmi, Matthias Parallel and Distributed Systems GMD Laboratory GMD-FIRST Rudower Chaussee 5 BerlinD-12489 Germany Computer Architecture and Parallel Systems Laboratory University of Delaware 140 Evans Hall NewarkDE19716 United States

ISBN: (纸本)0897919696

a key issue of problem-oriented parallel programming is an appropriate concept for representing the spatial structures of an application and modelling local or global interactions operating on them. This paper advocates for the use of so-called index spaces as a unified and powerful expression tool. It discusses the interface between application modelling and programming abstractions, and presents their embeddings in the high-level, data parallel language Promoter. © 1998 ACM.

关键词： Parallel programming

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