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检索条件"机构=Computer Architecture and Systems Laboratory"

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Verification of self-checking properties by means of output code space computation

Verification of self-checking properties by means of output ...

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European Conference on Design Automation

作者： M. Nicolaidis M. Boudjit Reliable Integrated Systems Group Computer Architecture IMAG/TIMA Laboratory Grenoble France

In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from the blocks feeding their inputs (i.e. the code word output spaces of the source blocks). In a complex system the computation of the output spaces by means of exhaustive simulation of the system is intractable. The paper presents a tool which performs this computation with low CPU time. This tool is a part of PROTECT, a tool which is aimed at automatic generation of complex self-checking circuits.< >

关键词： Circuit faults Protection Hardware Circuit testing Electrical fault detection Fault detection Encoding computer architecture Central Processing Unit Programming

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Behaviour driven development for hardware design

Behaviour driven development for hardware design

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作者： Diepenbeck, Melanie Kühne, Ulrich Soeken, Mathias Grosse, Daniel Drechsler, Rolf Group of Computer Architecture University of Bremen Germany LTCI Télécom ParisTech Université Paris-Saclay Paris France Integrated Systems Laboratory EPFL Lausanne Switzerland CPS DFKI Bremen Germany

Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers. Hence, one of the biggest challenges in design and verification today is to find new ways to increase the productivity. For software development the agile methodology as an incremental approach has been proposed and is heavily used. Behavior Driven Development (BDD) as an agile technique additionally enables a direct link to natural language based testing. In this article, we show how BDD can be extended to make it viable for hardware design. In addition, we present a two-fold strategy which allows to specify textual acceptance tests and textual formal properties. Finally, this strategy is complemented by methods to generalize tests to properties, and to enhance design understanding by presenting debug and witness scenarios in natural language. © 2018 Information Processing Society of Japan.

关键词： Acceptance tests

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ZnG: Architecting GPU Multi-Processors with New Flash for Scalable Data Analysis

ZnG: Architecting GPU Multi-Processors with New Flash for Sc...

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Annual International Symposium on computer architecture, ISCA

作者： Jie Zhang Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST)

ISBN: (数字)9781728146614

ISBN: (纸本)9781728146621

We propose ZnG, a new GPU-SSD integrated architecture, which can maximize the memory capacity in a GPU and address performance penalties imposed by an SSD. Specifically, ZnG replaces all GPU internal DRAMs with an ultra-low-latency SSD to maximize the GPU memory capacity. ZnG further removes performance bottleneck of the SSD by replacing its flash channels with a high-throughput flash network and integrating SSD firmware in the GPU's MMU to reap the benefits of hardware accelerations. Although flash arrays within the SSD can deliver high accumulated bandwidth, only a small fraction of such bandwidth can be utilized by GPU's memory requests due to mismatches of their access granularity. To address this, ZnG employs a large L2 cache and flash registers to buffer the memory requests. Our evaluation results indicate that ZnG can achieve 7.5× higher performance than prior work.

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GraphTensor: Comprehensive GNN-Acceleration Framework for Efficient Parallel Processing of Massive Datasets

GraphTensor: Comprehensive GNN-Acceleration Framework for Ef...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Junhyeok Jang Miryeong Kwon Donghyun Gouk Hanyeoreum Bae Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST)

We present GraphTensor, a comprehensive open-source framework that supports efficient parallel neural network processing on large graphs. GraphTensor offers a set of easy-to-use programming primitives that appreciate both graph and neural network execution behaviors from the beginning (graph sampling) to the end (dense data processing). Our framework runs diverse graph neural network (GNN) models in a destination-centric, feature-wise manner, which can significantly shorten training execution times in a GPU. In addition, GraphTensor rearranges multiple GNN kernels based on their system hyperparameters in a self-governing manner, thereby reducing the processing dimensionality and the latencies further. From the end-to-end execution viewpoint, GraphTensor significantly shortens the service-level GNN latency by applying pipeline parallelism for efficient graph dataset preprocessing. Our evaluation shows that GraphTensor exhibits 1.4× better training performance than emerging GNN frameworks under the execution of large-scale, real-world graph workloads. For the end-to-end services, GraphTensor reduces training latencies of an advanced version of the GNN frameworks (optimized for multi-threaded graph sampling) by 2.4×, on average.

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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations

A parallel Ray Tracing architecture suitable for application...

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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands

ISBN: (纸本)9780769544946

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared." © 2011 IEEE.

关键词： Ray tracing

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Fast Energy Estimation Through Partial Execution of HPC Applications 29

Fast Energy Estimation Through Partial Execution of HPC Appl...

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29th IEEE International Conference on Application-Specific systems, architectures and Processors, ASAP 2018

作者： Salinas-Hilburg, Juan Carlos Zapater, Marina Moya, Jose M. Ayala, Jose L. Dept. of Computer Architecture and Automation Complutense University of Madrid Madrid Spain Lausanne Switzerland Integrated Systems Laboratory Technical University of Madrid Madrid Spain CCS-Center for Computational Simulation Madrid Spain

ISBN: (纸本)9781538674796

In order to optimize the energy use of servers in Data Centers, techniques such as power capping or power budgeting are usually deployed. These techniques rely on the prediction of the power and execution time of applications. These data are obtained via dynamic profiling which requires a full execution of the application. This is not feasible in High Performance Computing (HPC) applications with long execution times. In this paper, we present a methodology to estimate the dynamic CPU and memory energy consumption of an application without executing it completely. Our methodology merges static code analysis information and dynamic profiling via the partial execution of the application. We do so by leveraging the concept of application signature, defined as a reduced version of the application in terms of execution time and power profile. We validate our methodology with a set of CPU -intensive, memory-intensive benchmarks and multi-threaded applications in a presently shipping enterprise server. Our energy estimation methodology shows an overall error below 8.0% when compared to the dynamic energy of the whole execution of the application. Also, our energy estimation methodology allows to estimate the energy of multi-threaded applications with an RMSE equal to 12.7% when compared to the dynamic energy from the complete parallel execution. © 2018 IEEE.

关键词： Budget control

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HP's PA7100LC: a low-cost superscalar PA-RISC processor

HP's PA7100LC: a low-cost superscalar PA-RISC processor

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IEEE Compcon

作者： P. Knebel B. Arnold M. Bass W. Kever J.D. Lamb R.B. Lee P.L. Perez S. Undy W. Walker Information Systems Laboratory Hewlett Packard Company Fort Collins CO USA Computer Systems Architecture Laboratory Cupertino CA USA

Describes a new low-cost, superscalar PA-RISC processor including two integer arithmetic and logic units, a floating-point coprocessor, and a memory and I/O controller on a single VLSI chip. It implements the full PA-RISC1.1 functionality and adds several new features, including little-endian capability, uncacheable memory pages, and new multimedia instructions. The chip is fabricated in 0.8- mu m, three-level metal CMOS and is designed to run from 0 to 75 MHz. The cache system consists of an off-chip combined instruction/data cache ranging from 8 kByte to 2 MByte and a small on-chip instruction buffer. Memory consists of 4 MByte to 2 GByte of standard DRAMs or SIMMs (single in-line memory modules) connecting directly to the processor chip. The chip achieves performance levels comparable to those of previous generation high-end workstations while lowering overall system cost and power consumption to make possible a new generation of low-cost systems.< >

关键词： Power generation Floating-point arithmetic CMOS logic circuits Coprocessors Very large scale integration System-on-a-chip Joining processes Workstations Costs Energy consumption

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System-level runtime mapping exploration of reconfigurable architectures

System-level runtime mapping exploration of reconfigurable a...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Kamana Sigdel Mark Thompson Andy D. Pimentel Carlo Galuzzi Koen Bertels Computer Engineering Laboratory Delft University of Technology The Netherlands Computer Systems Architecture Group University of Amsterdam The Netherlands

Dynamic reconfigurable systems can evolve under various conditions due to changes imposed either by the architecture, or by the applications, or by the environment. In such systems, the design process becomes more sophisticated as all the design decisions have to be optimized in terms of runtime behaviors and values. Runtime mapping exploration allows to explore reconfigurable systems at runtime to optimize task mappings in order to adapt to the changing behavior of the application(s), the architecture, or the environment. Performing such explorations at runtime enables a system to be more efficient in terms of various design constraints such as performance, chip area, power consumption, etc. Towards this goal, in this paper, we present a model that facilitates runtime mapping exploration of reconfigurable architectures. A case study of an MJPEG application shows that the presented model can be used to perform runtime exploration of various functional and non-functional design parameters.

关键词： Reconfigurable architectures Runtime environment computer architecture Process design Design optimization Energy consumption Power system modeling Embedded system Hardware Embedded computing

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Implementation of Neural Network-Based Nonlinear Adaptive Model Predictive Control over a Service-Oriented computer Network

Implementation of Neural Network-Based Nonlinear Adaptive Mo...

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American Control Conference

作者： Vincent A. Akpan Ioakeim K. Samaras George D. Hassapis Laboratory of Computer Systems Architecture Department of Electrical and Computer Engineering Aristotle University of Thessaloniki 54124 Thessaloniki Greece

ISBN: (纸本)9781424474264

This paper presents a new neural network-based nonlinear adaptive model predictive control algorithm and its implementation over a service-oriented computer network. The computer network is based on the device profile for web services. At each sampling instant, the algorithm identifies a nonlinear process model using a recurrent neural network. On the basis of the identified model, the nonlinear adaptive model predictive control is updated and the control actions are applied. The network training is performed with data obtained from the prior plant operation under different input disturbances. The proposed nonlinear model identification and nonlinear adaptive model predictive control were applied to the temperature control of a fluidized bed furnace reactor and tested by simulating the reactor operation on the proposed service-oriented computer network. Input step changes and long range output prediction results show good predictive and adaptive control performance. The computation time of the proposed algorithms running on the proposed network architecture was less than the sampling period of the process with a bounded round trip delay. These simulation results indicate that the proposed identification and control algorithms can be of practical use to processes with similar dynamics with the fluidized bed reactor. This is because their realization over a service-oriented computer network which may be the physical platform of their implementation does not introduce delays of such a level that may alter the required sampling time for good control performance.

关键词： computer network Adaptive Model device profile control performance Predictive control Temperature control procedural model Simulation results control action REACTOR OPERATION recurrent neural nets sampling time Fluidized bed reactors

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Way Sharing Set Associative Cache architecture

Way Sharing Set Associative Cache Architecture

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International Conference on VLSI Design

作者： C.J. Janraj T. Venkata Kalyan Tripti Warrier Madhu Mutyam Computer Architecture and Systems Laboratory Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai India

In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-way set-associative caches, irrespective of the set-wise demand, each set has n cache ways at its disposal, but cache sets may exhibit non-uniform demand for these cache ways. Exploiting this property, we propose a novel cache architecture, called way sharing cache, wherein by allowing sharing of cache ways among a pair of cache sets, we obtain dynamic energy savings as high as 41% in DL1 cache with negligible performance penalty.

关键词： Benchmark testing Shift registers Energy consumption Power demand Art Cache memory computer architecture

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