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检索条件"机构=Computer Architecture and Systems Laboratory"
294 条 记 录,以下是61-70 订阅
排序:
Verification of self-checking properties by means of output code space computation
Verification of self-checking properties by means of output ...
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European Conference on Design Automation
作者: M. Nicolaidis M. Boudjit Reliable Integrated Systems Group Computer Architecture IMAG/TIMA Laboratory Grenoble France
In complex self-checking systems several blocks (i.e. functional blocks and checkers) are embedded. In order to check the self-checking properties of such blocks one needs to know the set of vectors they receive from ... 详细信息
来源: 评论
Behaviour driven development for hardware design
Behaviour driven development for hardware design
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作者: Diepenbeck, Melanie Kühne, Ulrich Soeken, Mathias Grosse, Daniel Drechsler, Rolf Group of Computer Architecture University of Bremen Germany LTCI Télécom ParisTech Université Paris-Saclay Paris France Integrated Systems Laboratory EPFL Lausanne Switzerland CPS DFKI Bremen Germany
Hardware verification requires a lot of effort. A recent study showed that on average, there are more verification engineers working on a project than design engineers. Hence, one of the biggest challenges in design a... 详细信息
来源: 评论
ZnG: Architecting GPU Multi-Processors with New Flash for Scalable Data Analysis
ZnG: Architecting GPU Multi-Processors with New Flash for Sc...
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Annual International Symposium on computer architecture, ISCA
作者: Jie Zhang Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST)
We propose ZnG, a new GPU-SSD integrated architecture, which can maximize the memory capacity in a GPU and address performance penalties imposed by an SSD. Specifically, ZnG replaces all GPU internal DRAMs with an ult...
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GraphTensor: Comprehensive GNN-Acceleration Framework for Efficient Parallel Processing of Massive Datasets
GraphTensor: Comprehensive GNN-Acceleration Framework for Ef...
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International Symposium on Parallel and Distributed Processing (IPDPS)
作者: Junhyeok Jang Miryeong Kwon Donghyun Gouk Hanyeoreum Bae Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology (KAIST)
We present GraphTensor, a comprehensive open-source framework that supports efficient parallel neural network processing on large graphs. GraphTensor offers a set of easy-to-use programming primitives that appreciate ...
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A parallel Ray Tracing architecture suitable for application-specific hardware and GPGPU implementations
A parallel Ray Tracing architecture suitable for application...
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2011 14th Euromicro Conference on Digital System Design: architectures, Methods and Tools, DSD 2011
作者: Nery, Alexandre S. Nedjah, Nadia Franca, Felipe M.G. Jozwiak, Lech LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands
The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frame... 详细信息
来源: 评论
Fast Energy Estimation Through Partial Execution of HPC Applications  29
Fast Energy Estimation Through Partial Execution of HPC Appl...
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29th IEEE International Conference on Application-Specific systems, architectures and Processors, ASAP 2018
作者: Salinas-Hilburg, Juan Carlos Zapater, Marina Moya, Jose M. Ayala, Jose L. Dept. of Computer Architecture and Automation Complutense University of Madrid Madrid Spain Lausanne Switzerland Integrated Systems Laboratory Technical University of Madrid Madrid Spain CCS-Center for Computational Simulation Madrid Spain
In order to optimize the energy use of servers in Data Centers, techniques such as power capping or power budgeting are usually deployed. These techniques rely on the prediction of the power and execution time of appl... 详细信息
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HP's PA7100LC: a low-cost superscalar PA-RISC processor
HP's PA7100LC: a low-cost superscalar PA-RISC processor
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IEEE Compcon
作者: P. Knebel B. Arnold M. Bass W. Kever J.D. Lamb R.B. Lee P.L. Perez S. Undy W. Walker Information Systems Laboratory Hewlett Packard Company Fort Collins CO USA Computer Systems Architecture Laboratory Cupertino CA USA
Describes a new low-cost, superscalar PA-RISC processor including two integer arithmetic and logic units, a floating-point coprocessor, and a memory and I/O controller on a single VLSI chip. It implements the full PA-... 详细信息
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System-level runtime mapping exploration of reconfigurable architectures
System-level runtime mapping exploration of reconfigurable a...
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International Symposium on Parallel and Distributed Processing (IPDPS)
作者: Kamana Sigdel Mark Thompson Andy D. Pimentel Carlo Galuzzi Koen Bertels Computer Engineering Laboratory Delft University of Technology The Netherlands Computer Systems Architecture Group University of Amsterdam The Netherlands
Dynamic reconfigurable systems can evolve under various conditions due to changes imposed either by the architecture, or by the applications, or by the environment. In such systems, the design process becomes more sop... 详细信息
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Implementation of Neural Network-Based Nonlinear Adaptive Model Predictive Control over a Service-Oriented computer Network
Implementation of Neural Network-Based Nonlinear Adaptive Mo...
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American Control Conference
作者: Vincent A. Akpan Ioakeim K. Samaras George D. Hassapis Laboratory of Computer Systems Architecture Department of Electrical and Computer Engineering Aristotle University of Thessaloniki 54124 Thessaloniki Greece
This paper presents a new neural network-based nonlinear adaptive model predictive control algorithm and its implementation over a service-oriented computer network. The computer network is based on the device profile... 详细信息
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Way Sharing Set Associative Cache architecture
Way Sharing Set Associative Cache Architecture
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International Conference on VLSI Design
作者: C.J. Janraj T. Venkata Kalyan Tripti Warrier Madhu Mutyam Computer Architecture and Systems Laboratory Department of Computer Science and Engineering Indian Institute of Technology Madras Chennai India
In order to minimize the conflict miss rate, cache memories can be organized in set-associative manner. The downside of increasing the associativity is increase in the per access energy consumption. In conventional n-... 详细信息
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