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International Conference on Embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Dimitris Theodoropoulos Polyvios Pratikakis Dionisios Pnevmatikatos Computer Architecture and VLSI Systems Laboratory Institute of Computer Science Foundation for Research and Technology-Hellas Crete Greece

ISBN: (纸本)9781479901043

Recently, many software runtime systems have been proposed that allow developers to efficiently map applications to contemporary consumer electronic devices and high-performance academic processing platforms. Most of these runtime systems employ advanced scheduling techniques for automatic task assignment to all available processing elements. However, they focus on a particular environment and architecture, and it is not easy to port them to reconfigurable embedded MPSoCs. As a consequence, in the embedded community, researchers implement hardwired application-specific task schedulers, which can not be used by other embedded MPSoCs. To address this problem, in this paper we propose a lightweight runtime software framework for reconfigurable shared-memory MPSoCs, that integrate a master embedded processor connected to slave cores. Similarly to many of the aforementioned advanced runtime systems, we adopt a task-based programming model that uses simple, pragma-based annotations of the application software, in order to dynamically resolve task dependencies. Our runtime system supports heterogeneity in the hardware resources, and is also low-overhead to account for possible limitations in their processing capabilities and available on-chip memory. To evaluate our proposal, we have prototyped an MPSoC with seven slaves to a Xilinx ML605 FPGA board. We run three micro-benchmarks that achieve a performance speedup of 3.8x, 7x and 5.8x, and energy consumption of 27%, 14% and 18% respectively, compared to a single-core baseline system with no runtime support.

关键词： Runtime Software Hardware Real-time systems Field programmable gate arrays Processor scheduling Programming

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Building a personal high performance computer with heterogeneous processors

Building a personal high performance computer with heterogen...

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International Conference on Grid and Cloud Computing

作者： Li, Qiang Huo, Zhigang Sun, Ninghui National Research Center for Intelligent Computing Systems Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769543130

Personal high performance computer (PHPC) requires lower cost and high performance. The Teraflops PHPC systems with special accelerator units like GPGPU have been presented, but they have difficulties in programming, compatibility and applicability. In this paper, we present HPP-PHPC, a hybrid architecture of heterogeneous processors connected by non-coherent off-chip system bus. The performance of HPP-PHPC is ensured by special processors integrated with vector units and high-efficiency interconnection between heterogeneous processors. And by the adoption of general processors and features like global physical address space and synchronization semantics in hardware, HPP-PHPC is more compatible and convenient for massage passing and PGAS programming model. Also it is more applicable to most applications, including those with many execution branches. Initial results obtained from our prototype system have proved our design. © 2010 IEEE.

关键词： Semantics

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Transient event detection for nonintrusive load monitoring and demand side management using voltage distortion

Transient event detection for nonintrusive load monitoring a...

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21st Annual IEEE Applied Power Electronics Conference and Exposition, APEC '06

作者： Cox, Robert Leeb, Steven B. Shaw, Steven R. Norford, Leslie K. Laboratory for Electromagnetic and Electronic Systems Massachusetts Institute of Technology Cambridge MA 02139 Department of Electrical and Computer Engineering Montana State University Bozeman MT Department of Architecture Massachusetts Institute of Technology Cambridge MA 02139

ISBN: (纸本)0780395476

This paper describes a simple system that can be used for autonomous demand-side management in a load site such as a home or commercial facility. The system identifies the operation of individual loads using transient patterns observed in the voltage waveform measured at an electric service outlet. The theoretical foundation of the measurement process is introduced, and a preprocessor that computes short-time estimates of the spectral content of the voltage waveform is described. The paper presents several example measurements demonstrating the ability of the system to obtain estimates of the spectral content of the voltage waveform. © 2006 IEEE.

关键词： Electric loads

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Sprinkler: Maximizing resource utilization in many-chip solid state disks

Sprinkler: Maximizing resource utilization in many-chip soli...

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IEEE Symposium on High-Performance computer architecture

作者： Myoungsoo Jung Mahmut T. Kandemir Department of EE Computer Architecture and Memory Systems Laboratory Department of CSE The Pennsylvania State University

Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource utilization and achieving high performance without additional NAND flash chips. Specifically, Sprinkler relaxes parallelism dependency by scheduling I/O requests based on internal resource layout rather than the order imposed by the device-level queue. In addition, Sprinkler improves flash-level parallelism and reduces the number of transactions (i.e., improves transactionallocality) by over-committing flash memory requests to specific resources. Our extensive experimental evaluation using a cycle-accurate large-scale SSD simulation framework shows that a many-chip SSD equipped with our Sprinkler provides at least 56.6% shorter latency and 1.8 -2.2 times better throughput than the state-of-the-art SSD controllers. Further, it improves overall resource utilization by 68.8% under different I/O request patterns and provides, on average, 80.2% more flash-level parallelism by reducing half of the flash memory requests at runtime.

关键词： Nonvolatile memory Abstracts Proposals Portable computers Flash memories Single photon emission computed tomography Layout

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Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors 93

Hardware/software resolution of pipeline hazards in pipeline...

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IEEE International Conference on computer-Aided Design

作者： I.-J. Huang A.M. Despain Advanced Computer Architecture Laboratory Department of Electrical Engineering-Systems University of Southern California USA

ISBN: (纸本)9780818644900

One major problem in pipeline synthesis is the detection and resolution of pipeline hazards. We present a new solution to the problem in the domain of pipelined application-specific instruction set processors, based on hardware/software concurrent engineering approach. An extended taxonomy of inter-instruction dependencies is proposed for the analysis of pipeline hazards. Hardware/software resolution candidates are then associated with these dependencies. Algorithms using the taxonomy and the resolutions are developed to detect and resolve pipeline hazards, and to explore the hardware and software design space. Application benchmarks are used to evaluate the designs and guide the design decision. The power of these tools are demonstrated through the pipeline synthesis of two processors including industrial one. Compared with other approaches, our method achieves higher throughput, and provides a way to explore the hardware/software tradeoff. Our method can be combined with current approaches to achieve even higher performance since they are orthogonal.

关键词： Hardware Hazards Pipeline processing Taxonomy Delay Application software Throughput Space exploration computer architecture Laboratories

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Automatic-SSD: Full Hardware Automation over New Memory for High Performance and Energy Efficient PCIe Storage Cards

Automatic-SSD: Full Hardware Automation over New Memory for ...

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IEEE International Conference on computer-Aided Design

作者： Gyuyoung Park Myoungsoo Jung Computer Architecture and Memory Systems Laboratory Korea Advanced Institute of Science and Technology Daejeon Korea

ISBN: (数字)9781665423243

We propose Automatic-SSD that converts all storage management logic into hardware, which enable energy efficient, high performance fast memory based block storage. To achieve low operating power, Automatic-SSD directly reads or writes host-side data to underlying backend storage media without internal DRAM caches. To realize such DRAM-less approach with better performance and make it more energy efficient, Automatic-SSD also removes the internal processor(s) and firmware execution therein by fully automating the backend request management and data transfers over all pipelined hardware modules. We prototype Automatic-SSD on a middle-end FPGA custom board, employing massive numbers of phase change memories as representative of new memory technologies. Our evaluation results show that, compared to a conventional firmware-based approach, Automatic-SSD shows up 28.8× and 25.4× better bandwidth and latency behaviors, respectively, while consuming only 5% of the total energy, on overage.

关键词： Microprogramming Nonvolatile memory Hardware Phase change random access memory Memory management Power demand Media

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PDAS: Processor design automation system

PDAS: Processor design automation system

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European Design Automation Conference

作者： I. Pyo A.M. Despain Advanced Computer Architecture Laboratory Department of Electrical Engineering-Systems University of Southern California USA

The PDAS (Processor Design Automation System) is a new approach to design automation that uses formal methods to achieve a new level of design power and the ability to formally validate designs. The idea is to develop a design automation system which considers both microprocessor hardware design and design of the corresponding language compiler concurrently. Benchmark programs are used to motivate design decisions and optimize performance. Compiler optimizations are considered during the design of hardware. The system spans language design, compiler design, instruction set design, microarchitecture, and VLSI implementation.< >

关键词： Personal digital assistants Design automation Natural languages Specification languages Hardware Design optimization Process design Formal languages Concrete computer architecture

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Common substructure extraction of proteins by geometric invariants

Common substructure extraction of proteins by geometric inva...

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10th International Conference on computer-Aided Design and computer Graphics

作者： Xu, Dong Li, Hua Gu, Tongjun Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Center for Systems Biology Institute of Biophysics Chinese Academy of Sciences Graduate University Chinese Academy of Sciences

ISBN: (纸本)9781424415786

Structure alignment could help to find shape similarities between proteins and guide structure classification and fold recognition. Common substructure detection and extraction are especially important, for which could guide the biologist to discover binding site or active site. We represent each segment of alpha-carbon backbone by using dihedral angles and curve moment invariants. Then, local and global structure alignment could be performed by iterative closest point algorithm. Maximum common substructures between a pair of proteins or within a protein could be found. Active sites also could be detected by the proposed algorithm.

关键词： Proteins

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Evaluation of runtime task mapping heuristics with rSesame - a case study 10

Evaluation of runtime task mapping heuristics with rSesame -...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Kamana Sigdel Mark Thompson Carlo Galuzzi Andy D. Pimentel Koen Bertels Computer Engineering Laboratory EEMCS Delft University of Technnology Netherlands Computer Systems Architecture Group University of Amsterdam Netherlands

ISBN: (纸本)9783981080162

rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we want to evaluate the framework's characteristics by showing that it can easily and quickly model, simulate and compare a wide range of runtime mapping heuristics from various domains. A case study with a Motion-JPEG (MJPEG) application demonstrates that the presented model can be efficiently used to model and simulate a wide variety of mapping heuristics as well as to perform runtime exploration of various non-functional design parameters such as execution time, number of reconfigurations, area usage, etc.

关键词： Runtime Reconfigurable architectures Partitioning algorithms Streaming media Design engineering Laboratories computer architecture Computational modeling computer simulation Processor scheduling

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Sprinkler: Maximizing resource utilization in many-chip solid state disks

arXiv

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arXiv 2017年

作者： Jung, Myoungsoo Kandemir, Mahmut T. Computer Architecture and Memory Systems Laboratory Yonsei University Department of EECS Pennsylvania State University

Resource utilization is one of the emerging problems in many-chip SSDs. In this paper, we propose Sprinkler, a novel device-level SSD controller, which targets maximizing resource utilization and achieving high performance without additional NAND flash chips. Specifically, Sprinkler relaxes parallelism dependency by scheduling I/O requests based on internal resource layout rather than the order imposed by the device-level queue. In addition, Sprinkler improves flash-level parallelism and reduces the number of transactions (i.e., improves transactionallocality) by over-committing flash memory requests to specific resources. Our extensive experimental evaluation using a cycle-accurate large-scale SSD simulation framework shows that a many-chip SSD equipped with our Sprinkler provides at least 56.6% shorter latency and 1.8 2.2 times better throughput than the state-of-the-art SSD controllers. Further, it improves overall resource utilization by 68.8% under different I/O request patterns and provides, on average, 80.2% more flash-level parallelism by reducing half of the flash memory requests at runtime. Copyright © 2017, The Authors. All rights reserved.

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