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International Symposium on Electronic System Design (ISED)

作者： Vishal Shrivastav S. G. Vadlamudi P. P. Chakrabarti Dipankar Das Purnendu Sinha Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Kharagpur India Electrical and Software Architecture Group General Motors India Science Laboratory Bangalore India

ISBN: (纸本)9781467347044

Embedded control systems used in safety critical systems need to be robust to quality-faults such as shift, noise, and spikes. Methods for finding counterexamples (quality-faults whose injection leads to violation of fault-tolerance requirements) at an early stage of control system design were proposed in the literature. Given these counterexamples, control design should be improved such that it is quality-fault tolerant. In this paper, we propose an effective methodology for finding critical components in embedded control systems which are sensitive to quality-faults based on the given counterexamples, which is an important step towards improving the control design. Experimental results on the fault-tolerant fuel controller of Simulink library show the efficacy of proposed methodology.

关键词： critical components quality-faults robustness fault-tolerance embedded control systems control systems Crucial components Fault tolerance Robustness control systems design embedding FINDINGS

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Combined Measurement of the Higgs Boson Mass in pp Collisions at s=7 and 8 TeV with the ATLAS and CMS Experiments

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Physical Review Letters 2015年第19期114卷 191803-191803页

作者： G. Aad B. Abbott J. Abdallah O. Abdinov R. Aben M. Abolins O. S. AbouZeid H. Abramowicz H. Abreu R. Abreu Y. Abulaiti B. S. Acharya L. Adamczyk D. L. Adams J. Adelman S. Adomeit T. Adye A. A. Affolder T. Agatonovic-Jovin J. A. Aguilar-Saavedra S. P. Ahlen F. Ahmadov G. Aielli H. Akerstedt T. P. A. Åkesson G. Akimoto A. V. Akimov G. L. Alberghi J. Albert S. Albrand M. J. Alconada Verzini M. Aleksa I. N. Aleksandrov C. Alexa G. Alexander T. Alexopoulos M. Alhroob G. Alimonti L. Alio J. Alison S. P. Alkire B. M. M. Allbrooke P. P. Allport A. Aloisio A. Alonso F. Alonso C. Alpigiani A. Altheimer B. Alvarez Gonzalez D. Álvarez Piqueras M. G. Alviggi B. T. Amadio K. Amako Y. Amaral Coutinho C. Amelung D. Amidei S. P. Amor Dos Santos A. Amorim S. Amoroso N. Amram G. Amundsen C. Anastopoulos L. S. Ancu N. Andari T. Andeen C. F. Anders G. Anders J. K. Anders K. J. Anderson A. Andreazza V. Andrei S. Angelidakis I. Angelozzi P. Anger A. Angerami F. Anghinolfi A. V. Anisenkov N. Anjos A. Annovi M. Antonelli A. Antonov J. Antos F. Anulli M. Aoki L. Aperio Bella G. Arabidze Y. Arai J. P. Araque A. T. H. Arce F. A. Arduh J-F. Arguin S. Argyropoulos M. Arik A. J. Armbruster O. Arnaez V. Arnal H. Arnold M. Arratia O. Arslan A. Artamonov G. Artoni S. Asai N. Asbah A. Ashkenazi B. Åsman L. Asquith K. Assamagan R. Astalos M. Atkinson N. B. Atlay B. Auerbach K. Augsten M. Aurousseau G. Avolio B. Axen M. K. Ayoub G. Azuelos M. A. Baak A. E. Baas C. Bacci H. Bachacou K. Bachas M. Backes M. Backhaus E. Badescu P. Bagiacchi P. Bagnaia Y. Bai T. Bain J. T. Baines O. K. Baker P. Balek T. Balestri F. Balli E. Banas Sw. Banerjee A. A. E. Bannoura H. S. Bansil L. Barak S. P. Baranov E. L. Barberio D. Barberis M. Barbero T. Barillari M. Barisonzi T. Barklow N. Barlow S. L. Barnes B. M. Barnett R. M. Barnett Z. Barnovska A. Baroncelli G. Barone A. J. Barr F. Barreiro J. Barreiro Guimarães da Costa R. Bartoldus A. E. Barton P. Bartos A. Bassalat A. Basye R. L. Bates S. J. Batista J. R. Batley M. Battaglia M. Bauce F. Bauer H. S. Bawa J. B. Beach CPPM Aix-Marseille Université and CNRS/IN2P3 Marseille France Homer L. Dodge Department of Physics and Astronomy University of Oklahoma Norman Oklahoma USA Institute of Physics Academia Sinica Taipei Taiwan Institute of Physics Azerbaijan Academy of Sciences Baku Azerbaijan Nikhef National Institute for Subatomic Physics and University of Amsterdam Amsterdam Netherlands Department of Physics and Astronomy Michigan State University East Lansing Michigan USA Department of Physics University of Toronto Toronto Ontario Canada Raymond and Beverly Sackler School of Physics and Astronomy Tel Aviv University Tel Aviv Israel Department of Physics Technion: Israel Institute of Technology Haifa Israel CERN Geneva Switzerland Department of Physics Stockholm University Sweden The Oskar Klein Centre Stockholm Sweden INFN Gruppo Collegato di Udine Sezione di Trieste Udine Italy ICTP Trieste Italy AGH University of Science and Technology Faculty of Physics and Applied Computer Science Krakow Poland Physics Department Brookhaven National Laboratory Upton New York USA Department of Physics Northern Illinois University DeKalb Illinois USA Fakultät für Physik Ludwig-Maximilians-Universität München München Germany Particle Physics Department Rutherford Appleton Laboratory Didcot United Kingdom Oliver Lodge Laboratory University of Liverpool Liverpool United Kingdom Institute of Physics University of Belgrade Belgrade Serbia Laboratorio de Instrumentacao e Fisica Experimental de Particulas-LIP Lisboa Portugal Departamento de Fisica Teorica y del Cosmos and CAFPE Universidad de Granada Granada (Spain) Portugal Department of Physics Boston University Boston Massachusetts USA Joint Institute for Nuclear Research JINR Dubna Dubna Russia INFN Sezione di Roma Tor Vergata Roma Italy Dipartimento di Fisica Università di Roma Tor Vergata Roma Italy Fysiska institutionen Lunds universitet Lund Sweden International Center for Elementary Particle Physics and Depart

A measurement of the Higgs boson mass is presented based on the combined data samples of the ATLAS and CMS experiments at the CERN LHC in the H→γγ and H→ZZ→4ℓ decay channels. The results are obtained from a simultaneous fit to the reconstructed invariant mass peaks in the two channels and for the two experiments. The measured masses from the individual channels and the two experiments are found to be consistent among themselves. The combined measured mass of the Higgs boson is mH=125.09±0.21 (stat)±0.11 (syst) GeV.

关键词： HIGGS bosons RESEARCH COLLISIONS (Nuclear physics) ATLAS (computer program language) REST mass (Relativity) BOSONS

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GPU vs FPGA: Example application on white light interferometry

GPU vs FPGA: Example application on white light interferomet...

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2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

作者： Pacholik, A. Müller, M. Fengler, W. Machleidt, T. Franke, K.-H. Computer Architecture and Embedded Systems Group Ilmenau University of Technology 98684 Ilmenau Germany Computer Graphics Group Ilmenau University of Technology 98684 Ilmenau Germany

ISBN: (纸本)9780769545516

High performance image processing applications area challenging field when targeting embedded processing. Field programmable gate arrays (FPGA) receive a growing interest as implementation platforms, but these solutions have to compete with the state of the art in image processing, which is codefined by graphics processing units (GPU). This paper provides a case study which analyzes the potential of embedded or hybrid implementation on FPGA and GPU for image stack processing in a white light interferometry (WLI) application. © 2011 IEEE.

关键词： Graphics processing unit

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Custom instruction hardware integration within a SoC hybrid environment

Custom instruction hardware integration within a SoC hybrid ...

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6th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2011

作者： Parri, Jonathan Bolic, Miodrag Groza, Voicu University of Ottawa School of Information Technology and Engineering Computer Architecture Research Group Canada

ISBN: (纸本)9781424491094

Traditionally, common processor augmentation solutions have involved the addition of coprocessors or the datapath integration of custom instructions within extensible processors as Instruction Set Extensions (ISE). Rarely is the hybrid option of using both techniques explored. Much research already exists concerning the identification and selection of custom hardware blocks from hardware/software partitioning techniques, but the question of how to best use this hardware within a user system where both coprocessors and datapath augmentations are possible remains. This paper looks to extend existing ISE algorithms which provide custom hardware as dataflow graphs (DFG) and place them appropriately within a hybrid System-on-Chip (SoC) using standard combinatorial optimization techniques. A combinatorial model is presented to address this placement issue and is applied to two well known kernel programs. We further show that such standard techniques can execute within a reasonable time frame alleviating the need for heuristics. © 2011 IEEE.

关键词： System-on-chip

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ASIPs for artificial neural networks

ASIPs for artificial neural networks

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6th IEEE International Symposium on Applied Computational Intelligence and Informatics, SACI 2011

作者： Shapiro, Daniel Parri, Jonathan Desmarais, John-Marc Groza, Voicu Bolic, Miodrag University of Ottawa School of Information Technology and Engineering Computer Architecture Research Group Canada

ISBN: (纸本)9781424491094

Customized application-specific processors called ASIPs are becoming commonplace in contemporary embedded system designs. Neural networks are an interesting application for which an ASIP can be tailored to increase performance, lower power consumption and/or increase throughput. Here, both the bidirectional associative memory and hopfield auto-associative memory networks are run through an automated instruction-set identification algorithm to identify and select custom instruction candidates suitable for neural network applications. Clusters of neural networks are highly parallel, and therefore it is interesting to consider a homogeneous multiprocessor composed of ASIPs. The two legacy neural network applications showed a 18120% improvement with the automatic hardware/software partitioning for a uniprocessor ASIP. However, due to pointers and function calling which did not resolve to hardware, the acceleration was concentrated in the network initialization part of the code. © 2011 IEEE.

关键词： Memory architecture

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LiSARD: LabVIEW integrated softcore architecture for reconfigurable devices

LiSARD: LabVIEW integrated softcore architecture for reconfi...

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2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

作者： Pacholik, A. Klockner, J. Muller, M. Gushchina, I. Fengler, W. Computer Architecture and Embedded Systems Group Ilmenau University of Technology 98684 Ilmenau Germany

ISBN: (纸本)9780769545516

The development of industrial control and measurement systems is often based on modular commercial off the-shelf hardware. Lately, for these platforms reconfigurable I/O modules with field-programmable gate arrays (FPGA) have gained significance, since they allow the implementation of data processing functionality very close to the data acquisition interfaces. However, algorithm complexity and floating-point support are limited by FGPA resources and design methods. This contribution presents an application specific configurable DSP soft core architecture built around a scalable double precision floating-point arithmetic/logic unit. The core can be seamlessly utilized as a functional component in Lab VIEW based FPGA designs. A small case study shows the performance of an example application implemented on the presented core in comparison to other embedded architectures. © 2011 IEEE.

关键词： Digital arithmetic

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Transactional conflict decoupling and value prediction 11

Transactional conflict decoupling and value prediction

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Proceedings of the international conference on Supercomputing

作者： Tabba, Fuad Hay, Andrew W. Goodman, James R. Architecture Technology Group Oracle Corporation United States Computer Science Department University of Auckland New Zealand

ISBN: (纸本)9781450301022

This paper explores data speculation for improving the performance of Hardware Transactional Memory (HTM). We attempt to reduce transactional conflicts by decoupling them from cache coherence conflicts;many HTMs do not distinguish between transactional conflicts and coherence conflicts, leading to false transactional conflicts. We also attempt to mitigate the effects of coherence conflicts by using value prediction in transactions. We show that coherence decoupling and value prediction in transactions complement each other, because they both speculate on data in ways that are infeasible in the absence of HTM support. As a demonstration of how data speculation can improve performance, we introduce DPTM, a best-effort HTM that mitigates the effects of false sharing at the cache line level. DPTM does not alter the underlying cache coherence protocol, and requires only minor, processor-local, modifications. We evaluate DPTM against a baseline best-effort HTM, and compare it with data restructuring by padding, the most commonly used method to avoid false sharing. Our experiments show that DPTM can dramatically improve performance in the presence of false sharing without degrading performance in its absence, and consistently performs better than restructuring by padding. © 2011 ACM.

关键词： Forecasting

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High-efficient architecture of Godson-T many-core processor 23

High-efficient architecture of Godson-T many-core processor

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23rd IEEE Hot Chips Symposium, HCS 2011

作者： Fan, Dongrui Zhang, Hao Wang, Da Ye, Xiaochun Song, Fenglong Zhang, Junchao Fan, Lingjun Advanced Micro-System Group National Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and targeted markets for AMS's Godson-T microprocessor...

ISBN: (纸本)9781467388771

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An integrated approach for identity and access management in a SOA context 11

An integrated approach for identity and access management in...

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Proceedings of the 16th ACM symposium on Access control models and technologies

作者： Hummer, Waldemar Gaubatz, Patrick Strembeck, Mark Zdun, Uwe Dustdar, Schahram Distributed Systems Group Information Systems Institute Vienna University of Technology Austria Software Architecture Group Faculty of Computer Science University of Vienna Austria Information Systems Institute Vienna University of Economics and Business Austria

ISBN: (纸本)9781450307215

In this paper, we present an approach for identity and access management (IAM) in the context of (cross-organizational) serviceoriented architectures (SOA). In particular, we defined a domainspecific language (DSL) for role-based access control (RBAC) that allows for the definition of IAM policies for SOAs. For the application in a SOA context, our DSL environment automatically produces WS-BPEL (Business Process Execution Language for Web services) specifications from the RBAC models defined in our DSL. We use the WS-BPEL extension mechanism to annotate parts of the process definition with directives concerning the IAM policies. At deployment time, the WS-BPEL process is instrumented with special activities which are executed at runtime to ensure its compliance to the IAM policies. The algorithm that produces extended WS-BPEL specifications from DSL models is described in detail. Thereby, policies defined via our DSL are automatically mapped to the implementation level of a SOA-based business process. This way, the DSL decouples domain experts' concerns from the technical details of IAM policy specification and enforcement. Our approach thus enables (non-technical) domain experts, such as physicians or hospital clerks, to participate in defining and maintaining IAM policies in a SOA context. Based on a prototype implementation we also discuss several performance aspects of our approach. © 2011 ACM.

关键词： Web services

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Robust embedded software design through early analysis of quality faults 11

Robust embedded software design through early analysis of qu...

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Proceedings of the 4th India Software Engineering Conference

作者： Das, Dipankar Chakrabarti, P.P. Sinha, Purnendu Electrical and Software Architecture Group GM India Science Lab. Bangalore 560066 India Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Kharagpur 721302 India

ISBN: (纸本)9781450305594

While providing correct functionality has been the thrust of most software design efforts, embedded software poses several additional challenges. Among them is designing robust software which can tolerate inaccurate inputs (coming from degraded sensors), failure of software components, and wearing-out of electro-mechanical parts it controls. For this, a design space exploration is performed and several design options are evaluated for their ability to tolerate quality (or accuracy degradation) faults. While a model-based approach enables an early analysis of quality faults, modeling and analyzing the effects of quality faults is a challenge. In this work we propose a quality fault-tolerance analysis framework which is used on operation-level models of embedded software, and an abstraction of quality-faults suitable for this analysis. The proposed method consists of characterizing individual components of the model, and then using the pre-characterized behaviors to quickly evaluate the software design. Characterization is a one-time effort and results of the same can be reused when a new design is evaluated. This results in additional speedup of upto 6-10× faster evaluation of designs, thereby facilitating a quick early evaluation of design options.

关键词： Software design

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