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Parallel instruction set extension identification

Parallel instruction set extension identification

引用

2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2010

作者： Shapiro, Daniel Montcalm, Michael Bolic, Miodrag School of Information Technology and Engineering Computer Architecture Research Group University of Ottawa Canada

ISBN: (纸本)9781424486809

Modern embedded processors are often customized to accelerate native code. However, the design space exploration of hardware/software trade-offs is often time-intensive. To explore the design space of a processor's instruction set, simulations are utilized. Instruction set extension identification is usually performed by analyzing the basic blocks of an application in a linear fashion. We present an instruction set extension identification pass implemented in the COINS compiler which can simultaneously enumerate candidate instruction set extensions in multiple basic blocks. Using benchmarks such as FFT and Dijkstra we show a compiler execution improvement of time up to 53.7% compared to the traditional sequential approach. © 2010 IEEE.

关键词： Economic and social effects

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Migrating individuals and probabilistic models on dedas: A comparison on continuous functions

Migrating individuals and probabilistic models on dedas: A c...

引用

10th IASTED International Conference on Artificial Intelligence and Applications, AIA 2010

作者： Muelas, Santiago Mendiburu, Alexander LaTorre, Antonio Peña, José-María Dept. of Computer Systems Architecture and Technology Universidad Politécnica de Madrid Spain Intelligent Systems Group Dept. of Computer Architecture and Technology University of the Basque Country Spain

ISBN: (纸本)9780889868182

One of the most promising areas in which probabilistic graphical models have shown an incipient activity is the field of heuristic optimization and, in particular, in the Estimation of Distribution Algorithms (EDAs). EDAs constitute a well-known family of Evolutionary Computation techniques, similar to Genetic Algorithms. Due to their inherent parallelism, different research lines have been studied trying to improve EDAs from the point of view of execution time and/or accuracy. Among these proposals, we focus on the so-called island-based models. This approach defines several islands (EDA instances) running independently and exchanging information with a given frequency. The information sent by the islands can be a set of individuals or a probabilistic model. This paper presents a comparative study of both information exchanging techniques for a univariate EDA (UMDAg) over a wide set of parameters and problems -the standard benchmark developed for the IEEEWorkshop on Evolutionary Algorithms and other Metaheuristics for Continuous Optimization Problems of the ISDA 2009 Conference. The study concludes that the configurations based on migrating individuals obtain better results.

关键词： Computation theory

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Communication architectures for run-time reconfigurable modules in a 2-D mesh on FPGAs

Communication architectures for run-time reconfigurable modu...

引用

International Conference on Reconfigurable Computing and FPGAs

作者： Strunk, Jochen Hiltscher, Johannes Rehm, Wolfgang Schick, Heiko Computer Architecture Group Chemnitz University of Technology Chemnitz Germany Research and Development IBM Deutschland Research and Development GmbH Boeblingen Germany

ISBN: (纸本)9780769543147

This paper examines the feasibility of utilizing a 2-dimensional (2-D) mesh of run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA for throughput- and real-time-driven tasks. To utilize a 2-D mesh of RTRMs, efficient communication architectures (CA) are required, which will be presented in this work. Such a 2-D mesh of RTRMs on a DPR-capable FPGA can be utilized for throughput-driven tasks to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems, it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The exploration also includes a CA for real-time communication between RTRMs in a 2-D mesh. The presented CA design is based on a novel methodology by applying run-time reconfiguration to increase the performance. The design, the implementation, the performance and the resource utilization is shown for throughput- and real-time-driven CAs. As proof of concept, a case study is conducted for the presented CAs on state of the art Virtex-5 FPGAs. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Design of an introductory networking subject in advance of the European Higher Education Area: Challenges, experiences and open issues

Design of an introductory networking subject in advance of t...

引用

2010 IEEE Education Engineering Conference, EDUCON 2010

作者： Vallejo, Enrique García, Eduardo Group of Computer Architecture and Technology University of Cantabria Santander Spain Sistema 1 S.L University of Cantabria Santander Spain

ISBN: (纸本)9781424465682

The field of computer Networks has evolved quickly during the last years. In this paper we consider different aspects of those changes that condition the design of a subject in Networking;specifically, we discuss social, technological and economic aspects. Additionally, the changes proposed in the University studies for the European Higher Education Area condition the design of any current subject. Altogether, these changes condition the design and implementation of a subject on computer Networks. Considering the presented changes we sketch the design of an introductory subject on computer Networking. The subject is part of a pre-Bologna course, but is designed with the transition on mind. On the paper, we sketch the implementation of the course, designed to simplify the transition to conform the recommendations of the European Higher Education Area. We detail what contents were part of the theoretical or lab sessions, and how we managed to make most lab sessions with mid-class real hardware, introducing relatively complex concepts such as Quality of Service. © 2010 IEEE.

关键词： computer networks

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WCET tool challenge 2011: Report

WCET tool challenge 2011: Report

引用

11th International Workshop on Worst-Case Execution Time Analysis, WCET 2011, Held at the 23rd Euromicro Conference on Real-Time Systems

作者： Von Hanxleden, Reinhard Holsti, Niklas Lisper, Björn Ploedereder, Erhard Wilhelm, Reinhard Bonenfant, Armelle Cassé, Hugues Bünte, Sven Fellger, Wolfgang Gepperth, Sebastian Gustafsson, Jan Huber, Benedikt Islam, Nazrul Mohammad Kästner, Daniel Kirner, Raimund Kovács, Laura Krause, Felix De Michiel, Marianne Olesen, Mads Christian Prantl, Adrian Puffitsch, Wolfgang Rochange, Christine Schoeberl, Martin Wegener, Simon Zolda, Michael Zwirchmayr, Jakob Department of Computer Science Christian-Albrechts-Universität zu Kiel Olshausenstr. 40 24098 Kiel Germany Tidorum Ltd Tiirasaarentie 32 FI-00200 Helsinki Finland School of Innovation Design and Engineering Mälardalen University Västeras Sweden University of Stuttgart Universitätsstr. 38 71229 Stuttgart Germany FR. 6.2 - Computer Science Universität des Saarlandes PO-Box 15 11 50 66041 Saarbrücken Germany IRIT CNRS Université de Toulouse France Faculty of Informatics Technical University Vienna 1040 Vienna Austria AbsInt Angewandte Informatik GmbH Science Park 1 66123 Saarbrücken Germany Compiler Technology and Computer Architecture Group University of Hertfordshire Hatfield Hertfordshire AL10 9AB United Kingdom Department of Computer Science Aalborg University Selma Lagerlöfs Vej 300 9220 Aalborg Denmark Lawrence Livermore National Laboratory P.O. Box 808 Livermore CA 94551 United States Department of Informatics and Mathematical Modeling Technical University of Denmark Asmussens Alle DTU Building 305 2800 Lyngby Denmark

ISBN: (纸本)9781632663153

Following the successful WCET Tool Challenges in 2006 and 2008, the third event in this series was organized in 2011, again with support from the ARTIST DESIGN Network of Excellence. Following the practice established in the previous Challenges, the WCET Tool Challenge 2011 (WCC'11) defined two kinds of problems to be solved by the Challenge participants with their tools, WCET problems, which ask for bounds on the execution time, and flow-analysis problems, which ask for bounds on the number of times certain parts of the code can be executed. The benchmarks to be used in WCC'11 were debie1, PapaBench, and an industrial-strength application from the automotive domain provided by Daimler. Two default execution platforms were suggested to the participants, the ARM7 as "simple target" and the MPC5553/5554 as a "complex target," but participants were free to use other platforms as well. Ten tools participated in WCC'11: aiT, Astrée, Bound-T, FORTAS, METAMOC, OTAWA, SWEET, TimeWeaver, TuBound and WCA.

关键词： Benchmarking

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Benchmarking IP blacklists for financial botnet detection

Benchmarking IP blacklists for financial botnet detection

引用

International Conference on Information Assurance and Security

作者： Oro, David Luna, Jesus Felguera, Toni Vilanova, Marc Serna, Jetzabel ESecurity Research Group Barcelona Digital Technology Centre Barcelona Spain CSIRT La Caixa Barcelona Spain Computer Architecture Department Technical University of Catalonia Barcelona Spain

ISBN: (纸本)9781424474080

Every day, hundreds or even thousands of computers are infected with financial malware (i.e. Zeus) that forces them to become zombies or drones, capable of joining massive financial botnets that can be hired by well-organized cyber-criminals in order to steal online banking customers' credentials. Despite the fact that detection and mitigation mechanisms for spam and DDoS-related botnets have been widely researched and developed, it is true that the passive nature (i.e. low network traffic, fewer connections) of financial botnets greatly hinder their countermeasures. Therefore, cyber-criminals are still obtaining high economical profits at relatively low risk with financial botnets. In this paper we propose the use of publicly available IP blacklists to detect both drones and Command & Control nodes that are part of financial botnets. To prove this hypothesis we have developed a formal framework capable of evaluating the quality of a blacklist by comparing it versus a baseline and taking into account different metrics. The contributed framework has been tested with approximately 500 million IP addresses, retrieved during a one-month period from seven different well-known blacklist providers. Our experimental results showed that these IP blacklists are able to detect both drones and C&C related with the Zeus botnet and most important, that it is possible to assign different quality scores to each blacklist based on our metrics. Finally, we introduce the basics of a high-performance IP reputation system that uses the previously obtained blacklists' quality scores, in order to reply almost in real-time whether a certain IP is a member of a financial botnet or not. Our belief is that such a system can be easily integrated into e-banking anti-fraud systems. © 2010 IEEE.

关键词： Crime

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Patterns for measuring performance-related QoS properties in service-oriented systems 10

Patterns for measuring performance-related QoS properties in...

引用

17th Conference on Pattern Languages of Programs, PLoP 2010

作者： Oberortner, Ernst Zdun, Uwe Dustdar, Schahram Distributed Systems Group Information Systems Institute Vienna University of Technology Austria Software Architecture Faculty of Computer Science Vienna University Austria Argentinierstrasse 8/184-1 1040 Vienna Austria

ISBN: (纸本)9781450301077

In service-oriented systems, clients can access services via a network. Service level agreements (SLA) can exist, which specify - among other things - performance-related Quality of Service (QoS) properties between the client and the server, such as round-trip time, processing time, or availability. For a service provider serious financial consequences or other penalties can follow in case of not fulfilling the SLAs. The service consumer wants to evaluate that the provider complies with the guaranteed SLAs. Designing and developing a QoS-aware service-oriented system means facing many design challenges, such as where and how to measure the performance-related QoS properties. This paper presents design practices and patterns for measuring such QoS properties by extending and utilizing existing patterns. The focus of the patterns lies on the QoS measuring impact on the client's or service's performance, the extend of separation of concerns, the property of reusability, and the preciseness of the measured QoS properties. The patterns help to build efficient solutions to measure performance-related QoS properties in a service-oriented system.

关键词： Quality of service

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Parallel instruction set extension identification

Parallel instruction set extension identification

引用

IEEE Convention of the Electrical and ELectronic Engineers in Israel

作者： Daniel Shapiro Michael Montcalm Miodrag Bolic School of Information Technology and Engineering Computer Architecture Research Group University of Ottawa Canada

关键词： Instruction sets Hardware Benchmark testing Optimization computer architecture

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Integrated system development process for high-precision motion control systems

Integrated system development process for high-precision mot...

引用

IEEE Conference on Control technology and Applications (CCTA)

作者： S. Zschäck A. Amthor M. Müller J. Klöckner Ch. Ament W. Fengler System Analysis Group Ilmenau University of Technology Ilmenau CO Germany Computer Architecture Group Ilmenau University of Technology Ilmenau CO Germany

A cost-efficient way to achieve high-accuracy motion control is the utilization of complex control algorithms. Hence advanced motion control constitutes a class of real-time applications, for which the technical feasibility strongly depends on the achievable execution performance on the embedded processing platform. The presented modular controller structure defines a set of advanced control algorithms able minimize the tracking error, even for friction affected kinematics. Transferring the controller design to an implementation-oriented modelling level focuses on minimizing the processing latency in order to realize the required high sample rate. The utilization or even the custom development of a parallel platform becomes inevitable, which is why it is necessary to integrate both, control and embedded platform development processes. The presented process includes controller design, platform mapping and architecture optimization to address the challenge of tailoring an application-specific modular embedded processing platform already on the modelling level before interfacing state-of-the-art tool chains.

关键词： Friction Trajectory Adaptation model Force Process control Mathematical model Hardware

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Design of an introductory networking subject in advance of the European Higher Education Area: Challenges, experiences and open issues

Design of an introductory networking subject in advance of t...

引用

IEEE Education Engineering (EDUCON)

作者： Enrique Vallejo Eduardo García Group of Computer Architecture and Technology University of Cantabria Santander Spain Sistema 1 S.L. University of Cantabria Santander Spain

The field of computer Networks has evolved quickly during the last years. In this paper we consider different aspects of those changes that condition the design of a subject in Networking; specifically, we discuss social, technological and economic aspects. Additionally, the changes proposed in the University studies for the European Higher Education Area condition the design of any current subject. Altogether, these changes condition the design and implementation of a subject on computer Networks. Considering the presented changes we sketch the design of an introductory subject on computer Networking. The subject is part of a pre-Bologna course, but is designed with the transition on mind. On the paper, we sketch the implementation of the course, designed to simplify the transition to conform the recommendations of the European Higher Education Area. We detail what contents were part of the theoretical or lab sessions, and how we managed to make most lab sessions with mid-class real hardware, introducing relatively complex concepts such as Quality of Service.

关键词： computer networks computer science education Hardware Laboratories Internet Quality of service Educational programs Europe Local area networks computer architecture

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