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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Jochen Strunk Johannes Hiltscher Wolfgang Rehm Heiko Schick Computer Architecture Group Chemnitz University of Technology Chemnitz Germany Research & Development M Deutschland Research and Development GmbH Boeblingen Germany

This paper examines the feasibility of utilizing a 2-dimensional (2-D) mesh of run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA for throughput- and real-time-driven tasks. To utilize a 2-D mesh of RTRMs, efficient communication architectures (CA) are required, which will be presented in this work. Such a 2-D mesh of RTRMs on a DPR-capable FPGA can be utilized for throughput-driven tasks to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems, it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The exploration also includes a CA for real-time communication between RTRMs in a 2-D mesh. The presented CA design is based on a novel methodology by applying run-time reconfiguration to increase the performance. The design, the implementation, the performance and the resource utilization is shown for throughput- and real-time-driven CAs. As proof of concept, a case study is conducted for the presented CAs on state of the art Virtex-5 FPGAs.

关键词： Field programmable gate arrays Routing computer architecture Real time systems Resource management Clocks Embedded systems

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Benchmarking IP blacklists for financial botnet detection

Benchmarking IP blacklists for financial botnet detection

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International Symposium on Information Assurance and Security (IAS)

作者： David Oro Jesus Luna Toni Felguera Marc Vilanova Jetzabel Serna Security Research Group Barcelona Digital Technology Centre Barcelona Spain La Caixa CSIRT Barcelona Spain Computer Architecture Department Technical University of Catalonia Barcelona Spain

Every day, hundreds or even thousands of computers are infected with financial malware (i.e. Zeus) that forces them to become zombies or drones, capable of joining massive financial botnets that can be hired by well-organized cyber-criminals in order to steal online banking customers' credentials. Despite the fact that detection and mitigation mechanisms for spam and DDoS-related botnets have been widely researched and developed, it is true that the passive nature (i.e. low network traffic, fewer connections) of financial botnets greatly hinder their countermeasures. Therefore, cyber-criminals are still obtaining high economical profits at relatively low risk with financial botnets. In this paper we propose the use of publicly available IP blacklists to detect both drones and Command & Control nodes that are part of financial botnets. To prove this hypothesis we have developed a formal framework capable of evaluating the quality of a blacklist by comparing it versus a baseline and taking into account different metrics. The contributed framework has been tested with approximately 500 million IP addresses, retrieved during a one-month period from seven different well-known blacklist providers. Our experimental results showed that these IP blacklists are able to detect both drones and C&C related with the Zeus botnet and most important, that it is possible to assign different quality scores to each blacklist based on our metrics. Finally, we introduce the basics of a high-performance IP reputation system that uses the previously obtained blacklists' quality scores, in order to reply almost in real-time whether a certain IP is a member of a financial botnet or not. Our belief is that such a system can be easily integrated into e-banking anti-fraud systems.

关键词： IP networks Bismuth Random access memory Measurement Banking Malware Real time systems

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Frequency dependent efficiency model of on-chip DC-DC buck converters

Frequency dependent efficiency model of on-chip DC-DC buck c...

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IEEE Convention of the Electrical and ELectronic Engineers in Israel

作者： Gregory Sizikov Avinoam Kolodny Eby G. Fridman Michael Zelikson Electrical Engineering Department Technion Technion-Israel Institute of Technology Haifa Israel Electrical and Computer Engineering Department University of Rochester Rochester NY USA Intel Architecture Group Intel Corporation Haifa Israel

An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. These converters feature high switching losses caused by the skin effect in the package inductors. The frequency dependent air-core inductor model is shown to be critical in determining the optimal switching frequency. A general RLC parameter extraction method is also described. Considering the skin effect results in a 15% reduction in overall DC-DC converter losses. The proposed approach focuses on decreasing ripple current related losses, which are dominant in the target operating condition. Consequently, to obtain optimal efficiency, the switching frequency increases as the load current decreases. An intuitive explanation for this surprising result is that switching losses rise linearly with frequency whereas ripple losses decrease as n 1.5 . A SPICE based circuit model of a DC-DC converter is applied to validate the proposed analytic method.

关键词： Inductors Switching frequency Analytical models Converters Load modeling Skin effect Frequency dependence

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rSesame - A generic system-level runtime simulation framework for reconfigurable architectures

rSesame - A generic system-level runtime simulation framewor...

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2009 International Conference on Field-Programmable technology, FPT'09

作者： Sigdel, Kamana Thompson, Mark Galuzzi, Carlo Pimentel, Andy D. Bertels, Koen Computer Engineering Group EEMCS Delft University of Technology Netherlands Computer Systems Architecture Group University of Amsterdam Netherlands

ISBN: (纸本)9781424443772

As reconfigurable architectures are gaining an increasing research and industrial attention, there is a significant need for intelligent tools and methodologies to assist designers with exploration and performance evaluation of such architectures. Towards this goal, we make a first attempt to present a generic system-level modeling and simulation framework which can explore and evaluate reconfigurable systems at design-time as well as at runtime. In this paper, we show the methodology behind the framework and study its key features. © 2009 IEEE.

关键词： Reconfigurable architectures

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PARBLO:Page-Allocation-Based DRAM Row Buffer Locality Optimization

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Journal of computer Science & technology 2009年第6期24卷 1086-1097页

作者：米伟冯晓兵贾耀仓陈莉薛京灵 Key Laboratory of Computer System and Architecture Institution of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new pageallocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% （with an average of 37.4%）. This reduction in row buffer miss rates will be translated into performance speedups by up to 15% （with an average of 5%）.

关键词： DRAM row buffer page allocation locality optimization

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The fifth international conference on intelligent environments (IE09): A report

The fifth international conference on intelligent environmen...

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作者： Callaghan, Vic Korneas, Achilles Royo, Dolors Reyes, Angelica Navarro, Leandro Computer Science University of Essex United Kingdom Inhabited Intel-ligent Environments Group United Kingdom Hellenic Open University Greece Computer Technology Institute Greece Technical University of Catalonia Spain Spain Techni-cal University of Catalonia Department of Computer Architecture Spain

The development of intelligent environments is considered an important step toward the realization of the ambient intelligence vision. Intelligent environments are technologically augmented everyday spaces that intuitively support human activity. The IE conferences traditionally provide a leading-edge forum for researchers and engineers to present their latest research and to discuss future directions in the area of intelligent environments. This article briefly presents the content of the Fifth International Conference on Intelligent Environments (IE09), which was held July 20-21 at the Castelldefels campus of the Technical University of Catalonia near Barcelona, Spain. Copyright © 2009, Association for the Advancement of Artificial Intelligence. All rights reserved.

关键词： Ambient intelligence

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System-level runtime mapping exploration of reconfigurable architectures

System-level runtime mapping exploration of reconfigurable a...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Kamana Sigdel Mark Thompson Andy D. Pimentel Carlo Galuzzi Koen Bertels Computer Engineering Laboratory Delft University of Technology The Netherlands Computer Systems Architecture Group University of Amsterdam The Netherlands

Dynamic reconfigurable systems can evolve under various conditions due to changes imposed either by the architecture, or by the applications, or by the environment. In such systems, the design process becomes more sophisticated as all the design decisions have to be optimized in terms of runtime behaviors and values. Runtime mapping exploration allows to explore reconfigurable systems at runtime to optimize task mappings in order to adapt to the changing behavior of the application(s), the architecture, or the environment. Performing such explorations at runtime enables a system to be more efficient in terms of various design constraints such as performance, chip area, power consumption, etc. Towards this goal, in this paper, we present a model that facilitates runtime mapping exploration of reconfigurable architectures. A case study of an MJPEG application shows that the presented model can be used to perform runtime exploration of various functional and non-functional design parameters.

关键词： Reconfigurable architectures Runtime environment computer architecture Process design Design optimization Energy consumption Power system modeling Embedded system Hardware Embedded computing

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Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA

Impact of run-time reconfiguration on design and speed - A c...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jochen Strunk Toni Volkmer Klaus Stephan Wolfgang Rehm Heiko Schick Computer Architecture Group Chemnitz University of Technology Germany IBM Deutschland Research and Development GmbH

This paper examines the feasibility of utilizing a grid of run-time reconfigurable (RTR) modules on a dynamically and partially reconfigurable (DPR) FPGA. The aim is to create a homogeneous array of RTR regions on a FPGA, which can be reconfigured on demand during run-time. We study its setup, implementation and performance in comparison with its static counterpart. Such a grid of partially reconfigurable regions (PRR) on a FPGA could be used as an accelerator for computers to offload compute kernels or as an enhancement of functionality in the embedded market which uses FPGAs. An in-depth look at the methodology of creating run-time reconfigurable modules and its tools is shown. Due to the lack of the tools in handling hundreds of dynamically reconfigurable regions a framework is presented which supports the user in the creation process of the design. A case study which uses state of the art Xilinx Virtex-5 FPGAs compares the run-time reconfigurable implementation and achievable clock speeds of a grid with up to 47 reconfigurable module regions with its static counterpart. For this examination a high performance module is used, which finds patterns in a bit stream (pattern matcher). This module is replicated for each partially reconfigurable region. Particularly, design considerations for the controller, which manages the modules, are introduced. Beyond this, the paper also addresses further challenges of the implementation of such a RTR grid and limitations of the reconfigurability of Xilinx FPGAs.

关键词： Runtime Field programmable gate arrays Embedded computing Grid computing Kernel Clocks Chemical technology computer architecture Process design Pattern matching

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An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication

An on Chip Network inside a FPGA for Run-Time Reconfigurable...

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Euromicro Symposium on Digital System Design

作者： Jochen Strunk Toni Volkmer Wolfgang Rehm Heiko Schick Computer Architecture Group Chemnitz University of Technology Germany IBM Deutschland Research and Development GmbH Germany

In this paper a low latency, on chip communication network (NoC) for a run-time reconfigurable (RTR) grid inside dynamically and partially reconfigurable (DPR) FPGAs is proposed, which supports the arbitrary placement of run-time reconfigurable modules (RTRM) inside the grid. The dedicated, fully meshed, silicon network should support the arrangement of communication channels between the RTRMs within the different partially reconfigurable regions (PRRs) on the FPGA. The design of the network guarantees a low latency communication of RTRMs without mutual interference of each other. In comparison with an implementation using FPGA resources the dedicated silicon network could save an huge amount of resources in terms of transistors. The new degree of parallel communication provided for a RTR grid with arbitrarily placeable RTRMs offers new application fields for DPR capable FPGAs. Multiple user applications with inter-communicating offload compute kernels can be loaded on a host coupled FPGA accelerator, a real-time (RT) system with concurrent communication tasks are possible and enhancing the functionality on demand for embedded systems is conceivable. A case study was conducted for proof of concept and for the verification of the run-time environment system, which manages the configurable network.

关键词： Network-on-a-chip Field programmable gate arrays Runtime Delay Silicon Communication networks Communication channels Interference Concurrent computing Embedded computing

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Efficient Java Communication Libraries over InfiniBand

Efficient Java Communication Libraries over InfiniBand

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Guillermo L. Taboada Juan Tourino Ramón Doallo Yao Lin Jizhong Han Computer Architecture Group University of A Coruña A Coruña Spain Institute of Computing Technology Chinese Academy of Sciences Beijing China

This paper presents our current research efforts on efficient Java communication libraries over InfiniBand. The use of Java for network communications still delivers insufficient performance and does not exploit the performance and other special capabilities (RDMA and QoS) of high-speed networks, especially for this interconnect. In order to increase its Java communication performance, InfiniBand has been supported in our high performance sockets implementation, Java Fast Sockets (JFS), and it has been greatly improved the efficiency of Java Direct InfiniBand (Jdib), our low-level communication layer, enabling zero-copy RDMA capability in Java. According to our experimental results, Java communication performance has been improved significantly, reducing start-up latencies from 34 mus down to 12 and 7 mus for JFS and Jdib, respectively, whereas peak bandwidth has been increased from 0.78 Gbps sending serialized data up to 6.7 and 11.2 Gbps for JFS and Jdib, respectively. Finally, it has been analyzed the impact of these communication improvements on parallel Java applications, obtaining significant speedup increases of up to one order of magnitude on 128 cores.

关键词： Java Libraries Sockets High-speed networks Delay Throughput computer architecture Bandwidth Design optimization Quality of service

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