检索结果-内蒙古大学图书馆

International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Jochen Strunk Toni Volkmer Wolfgang Rehm Heiko Schick Computer Architecture Group Chemnitz University of Technology Chemnitz Germany Research & Development IBM Deutschland Research and Development GmbH Boeblingen Germany

This paper examines the feasibility of utilizing a grid of asynchronously clocked run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA. In contrast to a synchronously clocked grid studied in research, the design, the implementation, the performance and the resource utilization of an asynchronously clocked grid is shown. Such a run-time reconfigurable (RTR) grid on a FPGA can be utilized to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The presented platform leverages synthesis and development constraints and is able to increase the overall throughput by allowing multiple clock domains within the grid. The performance and the additional resource utilization of handling multiple clock domains is compared to synchronously clocked grids. As proof of concept a case study with a grid of 47 RTRMs is conducted on state of the art Virtex-5 FPGAs.

关键词： Clocks Runtime Field programmable gate arrays Grid computing Resource management Network-on-a-chip Embedded system Throughput Engines Kernel

来源：评论

学校读者我要写书评

暂无评论

Adaptive video-on-demand broadcasting in ubiquitous computing environment

Adaptive video-on-demand broadcasting in ubiquitous computin...

引用

作者： Peng, Chao Tan, Yasuo Xiong, Naixue Yang, Laurence T. Park, Jong Hyuk Kim, Soon-Seok Network Architecture Group National Institute of Information and Communications Technology 4-2-1 Nukui-Kitamachi Koganei Tokyo 184-8795 Japan Graduate School of Information Science Japan Advanced Institute of Science and Technology 1-1 Asahidai Nomi Ishikawa 923-1292 Japan Department of Computer Science Georgia State University Atlanta GA United States Department of Computer Science St. Francis Xavier University Antigonish NS B2G 2W5 Canada Department of Computer Science and Engineering Kyungnam University Masan Korea Republic of Department of Computer Engineering Halla University Wonju Korea Republic of

Video-on-demand (VOD) is a service that allows users to view any video program from a server at the time of their choice, such kind of services are expected to be popular in future ubiquitous computing environment. Lots of broadcasting protocols for VOD services have been proposed, but they usually focus only on the tradeoff between bandwidth and delay, thus they are usually not efficient for the local storage. Since the ubiquitous network is heterogeneous and users will have different resource and communication capability, we need to address the storage issue in VOD systems. In this paper, we present several new effective broadcasting schemes, which can intelligently adjust the solution according to available bandwidth and local storage to achieve an ideal waiting time. © Springer-Verlag London Limited 2009.

关键词： Video on demand

来源：评论

学校读者我要写书评

暂无评论

Performance-aware speculation control using wrong path usefulness prediction

Performance-aware speculation control using wrong path usefu...

引用

2008 IEEE 14th International Symposium on High Performance computer architecture, HPCA 2008

作者： Chang, Joo Lee Kim, Hyesoon Mutlu, Onur Patt, Yale N. Department of Electrical and Computer Engineering University of Texas at Austin School of Computer Science Georgia Institute of Technology Computer Architecture Group Microsoft Research

ISBN: (纸本)9781424420704

Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrong-path (i.e. mis-speculated) instructions. These schemes assume that all wrong-path instructions are useless for processor performance and try to eliminate the execution of all wrong-path instructions. However, wrong-path memory references can be useful for performance by providing prefetching benefits for later correct-path operations. Therefore, eliminating wrong-path instructions without considering the usefulness of wrong-path execution can significantly reduce performance as well as increase overall energy consumption. This paper proposes a comprehensive, low-cost speculation control mechanism that takes into account the usefulness of wrong-path execution, while effectively reducing the energy consumption due to useless wrong-path instructions. One component of the mechanism is a simple, novel wrong-path usefulness predictor (WPUP) that can accurately predict whether or not wrong-path execution will be beneficial for performance. The other component is a novel branch-count based fetch gating scheme that requires very little hardware cost to detect if the processor is on the wrong path. The key idea of our speculation control mechanism is to gate the processor pipeline only if (1) the number of outstanding branches is above a dynamically-determined threshold and (2) the WPUP predicts that wrong-path execution will not be beneficial for performance. Our results show that our proposal eliminates most of the performance loss incurred by fetch gating mechanisms that assume wrong-path execution is useless, thereby both improving performance and reducing energy consumption while requiring very little (51-byte) hardware cost. ©2008 IEEE.

关键词： Energy utilization

来源：评论

学校读者我要写书评

暂无评论

Performance-aware speculation control using wrong path usefulness prediction

Performance-aware speculation control using wrong path usefu...

引用

IEEE Symposium on High-Performance computer architecture

作者： Chang Joo Lee Hyesoon Kim Onur Mutlu Yale N. Patt Department of Electrical and Computer Engineering University of Texas Austin USA School of Computer Science Georgia Institute of Technology Computer Architecture Group Microsoft Research

ISBN: (纸本)9781424420704

关键词： Prefetching Pipelines Hardware Engines Logic gates Energy consumption Benchmark testing

来源：评论

学校读者我要写书评

暂无评论

Multi-Hop Synchronization at the Application Layer of Wireless and Satellite Networks

Multi-Hop Synchronization at the Application Layer of Wirele...

引用

IEEE GLOBECOM 2008 - 2008 IEEE Global Telecommunications Conference

作者： A. Marco R. Casas J. L. Sevillano V. Coarasa J. L. Falco M. S. Obaidat Tecnodiscap group University of Zaragoza Spain Department of Computer Architecture and Technology University of Sevilla Spain Computer Science Department Monmouth University NJ USA

Time synchronization is a key issue in wireless and satellite networks; time-stamping collected data, tasks scheduling or efficient communications are just some applications. From all the existing techniques to achieve synchronization, those that work at the MAC layer and can precisely timestamp sync messages are the most accurate. However, working with standard protocols, usually prevents the user from accessing lower layers and consequently reduces accuracy. Receiver-receiver schema improves time-stamping performance because it eliminates the biggest non-deterministic error at the sender side; the medium access time. Nevertheless, utilization of these methods in multi- hop networks usually requires an extra amount of traffic. In this paper we present a method which allows accurate synchronization of large multi-hop networks such as satellite networks working at the application layer while keeping the message exchange to the minimum. Through an exhaustive experimentation, we show the protocol's performance and analyze the factors that influence synchronization accuracy the most.

关键词： Spread spectrum communication Frequency synchronization Satellite broadcasting Clocks Low earth orbit satellites Application software Performance analysis Time division multiple access Protocols Synthetic aperture radar interferometry

来源：评论

学校读者我要写书评

暂无评论

Editorial: Dependability and security

引用

IEEE Transactions on Dependable and Secure Computing 2008年第1期5卷 1-3页

作者： Iyer, Ravishankar K. Gligor, Virgil D. Kalbarczyk, Zbigniew T. Kanoun, Karama Katzenbeisser, Stefan Mukherjee, Shubu Shieh, Shiuhpyng Zorian, Yervant Department of Electrical and Computer Engineering Carnegie Mellon University Microsoft's Trusted Computing Academic Advisory Board Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign United States IEEE IEEE Computer Society LAAS CNRS IFIP Working Group 10.4 on Dependable Computing and Fault Tolerance Special Interest Group on Dependability Benchmarking IFIP Working Group 10.4 French SEE Technical Committee on Trustworthy Computer Systems SEE Working Group Design and Validation for Dependability Technical University Munich Germany Darmstadt University of Technology ACM IACR Intel's SER Tech Council Intel's Architecture Patent Committee Taiwan Information Security Center NCTU IEEE Reliability Society Taipei and Tainan IACR United States Virage Logic Corp. AT and T Bell Laboratories Logic Vision Inc. University of British Columbia IEEE Test Technology Technical Council

来源：评论

学校读者我要写书评

暂无评论

Using non-spatial prior information in block-matching based motion estimation

Using non-spatial prior information in block-matching based ...

引用

International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Tarik Arici Elif Albuz Yucel Altunbasak School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA Video Software Architecture Group NVIDIA Corporation Santa Clara CA USA

Due to memory bandwidth limitations and computational complexity considerations in hardware implementations, block matching combined with lscr 1 error norm and translational motion model is preferred in motion-estimation algorithms. Performance of this scheme is degraded by noise, compression artifacts, rotation, repeating structures, motion boundaries, zooming, and brightness changes. In this work, we present a Bayesian approach to incorporate prior information into block matching. Hypothesis testing is utilized to choose the most applicable prior motion vector and to compute a prior motion-vector distribution and its precision. Prior distribution is then updated with motion-vector likelihood derived from pixel data to obtain the posterior distribution, which is maximized via a search on the feasible motion-vector space.

关键词： Motion estimation Hardware Brightness Computational complexity Bayesian methods Testing Noise reduction Algorithm design and analysis Computational modeling Iterative algorithms

来源：评论

学校读者我要写书评

暂无评论

Mixed-radix twisted torus interconnection networks

Mixed-radix twisted torus interconnection networks

引用

21st International Parallel and Distributed Processing Symposium, IPDPS 2007

作者： Cámara, José M. Moretó, Miquel Vallejo, Enrique Beivide, Ramón Miguel-Alonso, José Martínez, Carmen Navaridas, Javier University of Burgos Dept. of Electromechanical Engineering Technical University of Catalonia Dept. of Computer Architecture University of Cantabria Computer Architecture Group University of the Basque Country Dept. of Computer Architecture and Technology

ISBN: (纸本)1424409101

Many parallel computers use Tori interconnection networks. Machines from Cray, HP and IBM, among others, exploit these topologies. In order to maintain full network symmetry, 2D and 3D Tori (k-ary 2-cubes and k-ary 3-cubes) must have the same number of nodes (k) per dimension resulting in square or cubic topologies. Nevertheless, for practical reasons, computer engineers have designed and built 2D and 3D Tori having a different number of nodes per dimension. These mixed-radix topologies are not edge-symmetric which translates into poor performance provoked by an unbalanced use of the network links. In this paper, we propose and analyze twisted 2D and 3D Tori which remove the network bottlenecks present in mixed-radix standard Tori. These new topologies recover edge-symmetry and, consequently, balance the utilization of their links. We describe the distance-related parameters of these twisted networks and use simulation to asses their performance under synthetic loads. The obtained results show noticeable and consistent performance gains (up to a 88% increase in accepted load). In addition, we propose scalable and practicable packet routing and folding techniques for these interconnection subsystems. The complexity of the resulting architectural solutions is similar to the one exhibited by traditional routing and folding mechanisms employed in standard Tori. This fact together with the performance improvements obtained could justify the use of these twisted topologies in the future. © 2007 IEEE.

关键词： Interconnection networks

来源：评论

学校读者我要写书评

暂无评论

Secure group communication in ad-hoc networks using tree parity machines 15

Secure group communication in ad-hoc networks using tree par...

引用

15th ITG/GI Symposium on Communication in Distributed Systems, KiVS 2007

作者： Saballus, Bjorn Volkmer, Markus Wallner, Sebastian System Architecture Group University of Karlsruhe KarlsruheD-76128 Germany Institute of Computer Technology Hamburg University of Technology HamburgD-21073 Germany

ISBN: (纸本)9783800729807

A fundamental building block of secure group communication is the establishment of a common group key. This can be divided into key agreement and key distribution. Common group key agreement protocols are based on the Diffie-Hellman (DH) key exchange and extend it to groups. group key distribution protocols are centralized approaches which make use of one or more special key servers. In contrast to these approaches, we present a protocol which makes use of the Tree Parity Machine key exchange between multiple parties. It does not need a centralized server and therefore is especially suitable for ad-hoc networks of any kind. © 2007 Institute of Electrical and Electronics Engineers *** Rights Reserved.

关键词： Ad hoc networks

来源：评论

学校读者我要写书评

暂无评论

On the necessity of combining coding with spacing and shielding for improving performance and power in very deep sub-micron interconnects

引用

17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007

作者： Murgan, T. Bacinschi, P.B. Pandey, S. Ortiz, A. García Glesner, M. Inst. of Microelectronic Systems Darmstadt Univ. of Technology Darmstadt Germany Group for Computer Architecture Univ. of Bremen Bremen Germany AnaFocus Seville Spain

ISBN: (纸本)9783540744412

In this work, the necessity of combining signal encoding schemes with low-level anti-crosstalk techniques like spacing and shielding is analyzed. It is shown that in order to increase the throughput improvement and/or reduce the power consumption, coding schemes should be integrated with layout techniques since methods like spacing and shielding can be regarded as very simple encoding schemes. On this basis, a theoretical framework for assessing the improvement in throughput and/or power consumption is constructed. Furthermore, several possibilities to integrate coding with classical anti-crosstalk techniques are discussed. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Shielding

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：