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Human systems integration and advanced technology in engineering department workload and manpower reduction

NAVAL ENGINEERS JOURNAL 2003年第1期115卷 57-65页

作者： Lively, KA Seman, AJ Kirkpatrick, M KENNETH A. LIVELY graduated from the University of Colorado with a BS in applied mathematics and an MS in mathematics in 1976 and from the Massachusetts Institute of Technology with an MS in electrical engineering and the degree ocean engineer in naval architecture and marine engineering in 1984. He retired from the U.S. Navy in 1989 after 23 years of service. Assignments included electrical officer on the USS Constellation (CV 64) project engineer for the DDG 51 machinery control system (NAVSEA) and DDG 51 Technical Director (NAVSEA). He was vice president of the PDI Division of Bird-Johnson Company from July 1989 to November 1998 where he managed various gas turbine and machinery controls related development projects. He joined Anteon Corporation's Systems Engineering Group as senior controls engineer in December 1998 where he provided technical support to the integrated power systems program (NAVSEA PMS 510) and managed the Office of Naval Research Afloat Laboratory. DR. MARK KIRKPATRICK is currently an independent consultant in human factors and work-load/manning analysis and modeling. He holds a Ph.D. degree in experimental psychology from The Ohio State University and has 34 years of experience in applied human factors. From 1982 through 2000 Dr. Kirkpatrick served as the senior vice president of Carlow International. Prior to joining Carlow in 1982 Dr. Kirkpatrick served as a member of the technical staff at North American Rockwell's Missiles Division and as a project director and vice president for Essex Corporation. His areas of expertise include workload simulation task analysis operator-in-the-loop simulation human performance experimentation statistical analysis and human factors T&E. He has directed and/or participated in human factors projects for the U.S. Navy U.S. Army NASA Department of Transportation the U.S. Nuclear Regulatory Commission and private industry. ANTHONY J. SEMAN III is the technical manager for the reduced ship's crew by virtual presence (RSVP) advanced technology d

Aboard current ships, such as the DDG 51, engineering control and damage control activities are manpower intensive. It is anticipated that, for future combatants, the workload demand arising from operation of systems under conditions of normal steaming and during casualty response will need to be markedly reduced via automated monitoring, autonomous control, and other technology initiatives. Current DDG 51 class ships can be considered as a manpower baseline and under Condition III typical engineering control involves seven to eight watchstanders at manned stations in the Central Control Station, the engine rooms and other machinery spaces. In contrast to this manning level, initiatives such as DD 21 and the integrated engineering plant (IEP) envision a partnership between the operator and the automation system, with more and more of the operator's functions being shifted to the automation system as manning levels decrease. This paper describes some human systems integration studies of workload demand reduction and, consequently, manning reduction that can be achieved due to application of several advanced technology concepts. Advanced system concept studies in relation to workload demand are described and reviewed including. Piecemeal applications of diverse automation and remote control technology concepts to selected high driver tasks in current DDG 51 activities. Development of the reduced ship's crew by virtual presence system that will provide automated monitoring and display to operators of machinery health, compartment conditions, and personnel health. The IEP envisions the machinery control system as a provider of resources that are used by various consumers around the ship. Resource needs and consumer priorities are at all times dependent upon the ship's current mission and the availability of equipment pawnbrokers.

关键词： Naval warfare

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Predictive classification for integrated pest management by clustering in NN output space

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6th International Work-Conference on Artificial and Natural Neural Networks, IWANN 2001

作者： Salmerón, M. Guidotti, D. Petacchi, R. Reyneri, L.M. Department of Computer Architecture and Technology E.T.S.I.I. Universidad de Granada Campus Fuentenuev a s/n GranadaE-18071 Spain Agricultural Sector Agricultural Entomology Section Scuola Superiore SantAnna Via Carducci 40 PisaI-56100 Italy Department of Electronics Politecnico di Torino c.so Duca degli Abruzzi 24 TorinoI-10129 Italy

ISBN: (纸本)9783540422372

In this paper we consider the successful hybridation of a two modern computational schemes, Clustering and Neural Networks, for the Predictive Classification of the future value of insect infestation levels for Integrated Pest Management (IPM) of olive groves. The predictive classification techniques employed allow managers to improve their work in two ways: first, by reducing sampling demands of the variables involved, which is a costly process;and second, by recognizing potential infestation problems a up to two weeks beforehand, in order to optimize the use of pesticide chemical products and this reduce financial costs. © Springer-Verlag Berlin Heidelberg 2001.

关键词： Artificial intelligence

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Industrial evaluation of DRAM SIMM tests

Industrial evaluation of DRAM SIMM tests

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IEEE International Test Conference

作者： Ad.J. van de Goor A. Paalvast Faculty of Information Technology and Systems Department of Electrical Engineering Section Computer Architecture and Digital Technique Delft University of Technnology Delft Netherlands

This paper describes the results of testing 50 single inline memory modules (SIMMs) each containing 16 16 Mbit DRAM chips (DUTs); 39 SIMMs failed, and of the 800 DUTs, 116 failed. In total 54 different test algorithms have been applied, using up to 168 different stress combinations for each test. The results show that GAL9R is the best test. Furthermore, it is shown that burst mode tests detect a completely different class of faults as compared with traditional word mode tests, and that tests with address scrambling enabled the detection of more faults.

关键词： Random access memory Stress Fault detection Production Performance evaluation Information technology computer architecture Electronic mail System testing Manuals

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Industrial evaluation of DRAM tests 99

Industrial evaluation of DRAM tests

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Proceedings of the conference on Design, automation and test in Europe

作者： Ad J. van de Goor J. de Neef Faculty of Information Technology and Systems Department of Electrical Engineering Section Computer Architecture and Digital Technique Delft University of Technology Delft The Netherlands

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Port interference faults in two-port memories

Port interference faults in two-port memories

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IEEE International Test Conference

作者： S. Hamdioui A.J. Van De Goor Intel Corporation Santa Clara CA USA Section Computer Architecture & Digital Technique Department of Electrical Engineering Faculty of Information Technology and Systems Delft University of Technnology Delft Netherlands

A two-port memory contains two similar ports, which can be accessed separately and independent of each other. In this paper, logical fault models are derived for the effect of shorts between the ports. The result is a... 详细信息

关键词： Interference Circuit faults Circuit testing Built-in self-test Educational institutions computer architecture Information technology Electronic mail Circuit simulation

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Industrial evaluation of DRAM tests

Industrial evaluation of DRAM tests

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Design, Automation and Test in Europe Conference and Exhibition

作者： A.J. van de Goer J. de Neef Dept. of Electr. Eng. Delft Univ. of Technol. Netherlands Faculty of Information Technology and Systems Department of Electrical Engineering Section Computer Architecture and Digital Technique Delft University of Technnology Delft Netherlands

This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i.e. those covering different functional faults) also have a higher fault coverage. However the currently used fault models still leave much to be explained; e.g., the used data backgrounds and address orders show an unexplainable large variation in fault coverage.

关键词： Random access memory Testing Stress Leakage current Indium phosphide Information technology computer architecture Postal services Hip Electronic switching systems

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Converting March tests for bit-oriented memories into tests for word-oriented memories

Converting March tests for bit-oriented memories into tests ...

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IEEE International Workshop on Memory technology, Design and Testing

作者： A.J. Van De Goor I.B.S. Tlili S. Hamdioui Section of Computer Architecture and Digital Technology Delft University of Technnology Delft Netherlands

In this paper a set of fault models for coupling faults between the cells of a word has been established, together with tests for these fault models. Thereafter, a systematic way of converting tests for bit-oriented memories into tests for word-oriented memories is presented, distinguishing between inter-word and intra-word faults. This results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.

关键词： System testing Satellite broadcasting Logic arrays Fault detection Information technology computer architecture Decoding Bills of materials

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March tests for word-oriented memories 98

March tests for word-oriented memories

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Design, Automation and Test in Europe Conference and Exhibition

作者： A.J. van de Goor I.B.S. Tlili Faculty of Information Technology and Systems Section Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

ISBN: (纸本)9780818683596

Most memory test algorithms are optimized tests for a particular memory technology, and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e., read and write operations affect only a single bit in the memory. Traditionally, word-oriented memories have been tested by repeated application of a test for bit-oriented memories whereby a different data background (which depends on the used intra-word fault model) is used during each iteration. This results in rime inefficiencies and limited fault coverage. A new approach for testing word-oriented memories is presented, distinguishing between inter-word and intra-word faults and allowing for a systematic way of converting tests for bit-oriented memories to rests for word-oriented memories. The conversion consists of concatenating the bit-oriented test for inter-word faults with a test for intra-word faults. This approach results in more efficient tests with complete coverage of the targeted faults. Because most memories have an external data path which is wider than one bit, word-oriented memory tests are very important.

关键词： System testing Satellite broadcasting Information technology computer architecture Electronic mail Electrical capacitance tomography Fault detection Legged locomotion Bills of materials

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Consequences of port restrictions on testing address decoder faults in two-port memories

Consequences of port restrictions on testing address decoder...

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Asian Test Symposium (ATS)

作者： S. Hamdioui A.J. van de Goor Faculty of Information Technology and Systems Department of Electrical Engineering Section of Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. This paper discusses the consequences of the port restrictions (read-only or write-only ports) on the tests; in addition it covers the test strategy for address decoder faults in two-port memories.

关键词： Decoding System testing Read-write memory computer architecture Electronic mail Performance evaluation Random access memory Interference

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Consequences of port restrictions on testing two-port memories

Consequences of port restrictions on testing two-port memori...

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IEEE International Test Conference

作者： S. Hamdioui A.J. van de Goor Faculty of Information Technology and Systems Department o Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible fault models, the tests for single-port and two-port memories, as well as the test strategy. This paper presents a test strategy for two-port memories and covers the consequences of the port restrictions (read-only or write-only ports).

关键词： Testing Logic arrays Random access memory Read-write memory Frequency conversion Logic devices Low voltage Conductivity Resource description framework

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