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IEEE International Test Conference

作者： S. Hamdioui A.J. van de Goor Faculty of Information Technology and Systems Department o Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technnology Delft Netherlands

Testing two-port memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible fault models, the tests for single-port and two-port memories, as well as the test strategy. This paper presents a test strategy for two-port memories and covers the consequences of the port restrictions (read-only or write-only ports).

关键词： Testing Logic arrays Random access memory Read-write memory Frequency conversion Logic devices Low voltage Conductivity Resource description framework

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Address decoder faults and their tests for two-port memories

Address decoder faults and their tests for two-port memories

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IEEE International Workshop on Memory technology, Design and Testing

作者： S. Hamdioui A.J. Van De Goer Faculty of Information Technology and Systems Section of Computer Architecture and Digital Technology Delft University of Technnology Delft Netherlands Technische Universiteit Delft Delft Zuid-Holland NL

A two-port memory contains two duplicated sets of address decoders which operate independently. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling ... 详细信息

关键词： Decoding Circuit faults Electronic switching systems Interference Electrical capacitance tomography Information technology computer architecture Built-in self-test Circuit testing Read-write memory

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March U: A test for unlinked memory faults

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IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 1997年第3期144卷 155-160页

作者： vandeGoor, AJ Gaydadjiev, GN Department of Electrical Engineering Section Computer Architecture & Digital Technique Delft University of Technology Mekelweg 4 Delft 2628 CD The Netherlands

Short and efficient memory tests is the goal of every test designer. To reduce the cost of production tests, often a simple test which covers most of the faults, e.g. all simple (unlinked) faults, is desirable to eliminate most defective parts;a more costly test can be used thereafter to eliminate the remainder of the bad parts. Such a test-cost efficient approach is used by most manufacturers. In addition, system power-on tests are not allowed a long test time while a high fault coverage is desirable. The authors propose a new realistic fault model (the disturb fault model), and a set of tests for unlinked faults. These tests have the property of covering all simple (unlinked) faults at a very reasonable test time compared with existing tests.

关键词： memory tests March tests memory faults fault model simple faults disturb fault

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Controlled node splitting 6th

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Proceedings of the 6th International Conference on Compiler Construction, CC'96

作者： Janssen, Johan Corporaal, Henk Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems 2600 GA Delft 5031 Netherlands

ISBN: (纸本)9783540610533

To exploit instruction level parallelism in programs over multiple basic blocks, programs should have reducible control flow graphs. However not all programs satisfy this property. A new method, called Controlled Node Splitting (CNS), for transforming irreducible control flow graphs to reducible control flow graphs is presented. CNS duplicates nodes of the control flow graph to obtain reducible control flow graphs. CNS results in a minimum number of splits and a minimum number of duplicates. Since the computation time to find the optimal split sequence is large, a heuristic has been developed. The results of this heuristic are close to the optimum. Straightforward application of node splitting may result in an average code size increase of 235%. CNS with the heuristic limits the increase to only 3%. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Compilation Control flow graphs Instruction level parallelism Irreducibility Node splitting Reducibility

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Identifying the capability of overlapping computation with communication

Identifying the capability of overlapping computation with c...

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International Conference on Parallel architecture and Compilation Techniques (PACT)

作者： A. Sohn J. Ku Y. Kodama M. Sato H. Sakane H. Yamana S. Sakai Y. Yamaguchi Computer and Information Science Department New Jersey Institute of Technology Newark NJ USA Computer Architecture Section Electro Technical Laboratory Tsukuba Ibaraki Japan Real World Computing Tsukuba Research Center Tsukuba Ibaraki Japan

Overlapping computation with communication is central to obtaining high performance on distributed-memory multiprocessors. This report explicates the overlapping capability of two distributed-memory multiprocessors: the EM-X and IBM SP-2. The well-known bitonic sorting algorithm is selected for experiments. Various message sizes are used to determine when, where, how much and why overlapping takes place. Experimental results indicate that both multiprocessors would yield up to 30% to 40% overlap of communication time when the message size is approximately 1K integers. EM-X is found to be message-size insensitive yielding high overlap for various message sizes, while SP-2 was effective for the window of message size 512 to 2K integers.

关键词： Delay computer architecture Switches Distributed computing High performance computing Sorting Prototypes Laboratories Yarn Windows

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Effects of multithreading on data and workload distribution for distributed-memory multiprocessors

Effects of multithreading on data and workload distribution ...

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International Symposium on Parallel Processing

作者： A. Sohn M. Sato Namhoon Yoo J.-L. Gaudiot Computer and Information Science Department New Jersey Institute of Technology Newark NJ USA Computer Architecture Section Electro Technical Laboratory Tsukuba Ibaraki Japan Department of EE-Systems University of Southern California Los Angeles CA USA

While data and workload distribution can be tailored to fit a particular problem to a particular distributed-memory architecture, it is often difficult to do so for various practical issues. This paper presents our study on multithreading for distributed-memory multiprocessors. Specifically, we investigate the effects of multithreading on data distribution and workload distribution with variable thread granularity. Various types of workload distribution strategies are defined along thread granularity. Three types of data distribution strategies are investigated: row-wise cyclic, k-way partial-row cyclic and blocked distribution. We have implemented all of these on the 80-processor EM-4 distributed-memory multiprocessor using highly-sequential Gaussian elimination with partial pivoting and highly-parallel matrix multiplication. Experimental results indicated that multithreading can offset the loss that is due to the mismatch of data distribution to workload distribution for even sequential and irregular problems while giving high absolute performance.

关键词： Multithreading Yarn Distribution strategy Performance loss

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Transport-triggering vs. Operation-triggering 5th

Transport-triggering vs. Operation-triggering

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5th International Conference on Compiler Construction, CC 1994

作者： Hoogerbrugge, Jan Corporaal, Henk Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems Netherlands

ISBN: (纸本)9783662466629

Transport-triggered architectures are a new class of architectures that provide more scheduling freedom and have unique compiler optimizations. This paper reports experiments that quantify the advantages of transport-triggered architectures with respect to traditional operation-triggered architectures. For the experiments we use an extended basic block scheduler that is currently being developed. The paper gives an description of the scheduling techniques used. The results of our experiments show that the extra scheduling freedom together with the new optimizations are very welcome when resource constraints are limiting the performance. This is the case when resources are scarce or when the application contains a lot of instruction level parallelism. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Scheduling

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Nonnumeric search results on the EM-4 distributed-memory multiprocessor 94

Nonnumeric search results on the EM-4 distributed-memory mul...

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Supercomputing Conference

作者： A. Sohn M. Sato S. Sakai Y. Kodama Y. Yamaguchi Computer and Information Science Department New Jersey Institute of Technology Newark NJ USA Computer Architecture Section Electro Technical Laboratory Tsukuba Ibaraki Japan

ISBN: (纸本)9780818666056

Numeric scientific problems have been the main focus of supercomputing as their numerous implementations on various multiprocessors indicate. Nonnumeric problems on the other hand have received very little attention for parallel implementation due to their irregular behaviors and a large amount of resource usage. This report presents our experiences implementing difficult nonnumeric problems on the EM-4 multiprocessor, believing that supercomputers should also be able to effectively execute nonnumeric problems if they are to be considered 'supercomputers'. We selected two typical search problems, the Eight-Puzzle and the Tower-of-Hanoi. Two parallel search techniques we used to implement the search problems, unidirectional and bidirectional heuristic search. A total of eight different programs have been implemented on the EM-4 multiprocessor with realistic problem sizes. Execution results demonstrate that the parallel bidirectional heuristic search can solve the tree depth 20 to 40 of the Eight-Puzzle in an optimal or near optimal number of iterations in less than two seconds, and is highly scalable as it gives over 40-fold speedup for both problems on 80 processors.< >

关键词： Concurrent computing Search problems Supercomputers Artificial intelligence Runtime Information science computer architecture Laboratories Buildings Parallel machines

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Parallel bidirectional heuristic search on the EM-4 multiprocessor

Parallel bidirectional heuristic search on the EM-4 multipro...

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International Symposium on Parallel and Distributed Processing (IPDPS)

Solving search problems takes a large amount of computational resources both in terms of execution time and memory usage. This report presents experimental results of Parallel Bidirectional Heuristic Search (PBiHS) on the 80-processor EM-4 multithreaded data-flow multiprocessor. The PBiHS searches from two directions in parallel while search in each direction is also performed in parallel. Important data structures are distributed to all processors to help reduce the execution time of realistic problem sizes down to a few seconds or less. We implement two search problems, the Eight Puzzle and the Tower of Hanoi, and execute on the target multiprocessor. Execution results demonstrate that the Parallel Bidirectional Heuristic Search can solve the tree depth 20-40 of the Eight-Puzzle and the 3-9 disks of the Tower of Hanoi in an optimal or near optimal number of iterations in less than two seconds, is highly scalable as it gives over 40-fold speedup on 80 processors, and yields on the average 10-fold improvement over unidirectional search for the 8-Puzzle while generating a far less number of nodes.< >

关键词： Search problems Poles and towers Artificial intelligence Concurrent computing Data structures Parallel processing Information science computer architecture Laboratories Buildings

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USING VIRTUAL ENVIRONMENTS IN THE DESIGN OF SHIPS

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NAVAL ENGINEERS JOURNAL 1994年第3期106卷 91-106页

作者： JONS, OP RYAN, JC JONES, GW Otto P. Jons:received a Diplom Ing. in shipbuilding from the Technical University of Hanover W. Germany and an MS in naval architecture and marine engineering from MIT. He then joined Litton Ship Systems where he was responsible for the preliminary design of the DD-963 hull structure and then for ship system integration as manager LHA ship systems engineering department. From 1972 to 1974 he was the principal research scientist at Hydronautics. In 1974 as technical director he helped establish the Crystal City office of Designers and Planners. Mr. Jons was one of the co-founders of Advanced Marine Enterprises Inc. in 1976 where he serves as corporate vice president engineering. J. Christopher Ryan:earned his bachelors and masters degrees in naval architecture from Webb Institute and MIT respectively. He spent three years at the advanced marine technology division of Litton Industries working on the DD-963 class ship design and related computer aided design projects. He subsequently went to the Navy Department concentrating on early stage design of surface combatants for twelve years including work on the FFG-7 Sea Control Ship CSGN and CVV aircraft carrier projects. He then shifted focus and became the Technical Director for the Computer Supported Design Program in NavSea for five years. Mr. Ryan has served in several supervisory positions within the Ship Design Group in NavSea since that time. He is currently the director of the future ship concepts division. Gary W. Jones:graduated from the University of Tennessee in 1971 with a BS in mechanical engineering and followed up with graduate work at George Washington University and the University of Maryland. Mr. Jones was with the Naval Sea Systems Command from 1971 until 1988 where he was a naval architect in the submarine section of the hull form design division. In 1988 he was detailed to the Defense Advanced Research Projects Agency (DARPA) where he became the program manager for the advanced submarine technology program's hydrodynamic hydroac

A major contributor to the expense and length of time to design, build, and test new systems has been the need to build and test hardware prototypes to determine their effectiveness in meeting operational requirements. Recent and dramatic advances in computer simulation technologies hold forth the promise of revolutionizing design and acquisition strategies by providing the means to validate end users' requirements prior to hardware construction. By designing and operationally testing virtual prototypes in a virtual environment, these technologies will soon offer naval architects the ability to build and launch ships in computer-based cyberspace in lieu of the shipbuilder's ways. The authors of this paper provide the background for these developments, explore the significance and ramifications of these technologies to the current process of ship and system design, outline challenges lying ahead, and present their vision and recommendations for future development.

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