This paper reports the results of a comparison between a new class of architectures, called transport-triggered architectures, and traditional architectures, called operation-t~iggered architectures. It does this comp...
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Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. This is achieved by clocking the system faster than the propagatio...
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作者:
LINDGREN, JRSOLITARIO, WAMOORE, APSTREIFF, MAJohn R. Lindgren
Jr:. is vice president for engineering at Ingalls Shipbuilding Inc. a Division of Litton Industries in Pascagoula Miss. He joined Ingalls in 1958 and has held various positions in the Engineering Division and participated in the design of numerous merchant ships drill rigs submarines and surface combatants and auxiliary support ships. Mr. Lindgren is a 1958 graduate of the University of Southwest Louisiana. His degree is in mechanical engineering and he is also a licensed professional engineer. William A. Solitario:is the director of advanced technology at Ingalls Shipbuilding
Inc. in Pascagoula Miss. He received his B.S. degree in chemical engineering from the City University of New York and has 28 years experience in marine engineering and design. His current responsibilities include the direction of Ingalls' IRAD programs and several Navy-funded R&D programs to improve ship's performance and reduce ship's operating costs. He is a member of the Society of Naval Architects and Marine Engineers and past chairman of the Gulf Section East Area. Arnold P. Moore:is the director
design engineering at Ingalls Shipbuilding where he is responsible for all new construction design and engineering activities. Prior to promotion to his current position Mr. Moore served as chief naval architect at Ingalls. He has 24 years experience in ship design construction and repair. Mr. Moore holds the professional degree of ocean engineer as well as a master's degree in naval architecture and marine engineering from MIT. He also earned a bachelor's degree in naval science from the U.S. Naval Academy and is a registered professional engineer. Mr. Moore served as an engineering duty officer in the U.S. Navy and is currently a captain in the Naval Reserve. He is a past chairman of the Gulf Section of the Society of Naval Architects and Marine Engineers and a member of the American Society of Naval Engineers and Sigma Xi. Michel A. Streiff:is the manager of CAD/CAM applications at Ingalls Shipbuilding
Inc. His
The SA'AR-5 Corvette Program is the first major warship construction to be entirely accomplished using a 3-dimensional, interference checked computer based design. This paper discusses the organization and approac...
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The SA'AR-5 Corvette Program is the first major warship construction to be entirely accomplished using a 3-dimensional, interference checked computer based design. This paper discusses the organization and approach used to create the design models which form the basis for interference checking as well as the source of extracted production data. The design or product model is the nucleus of the computer data base that defines the configuration of the entire ship. The data base includes geometry, weight, and material, as well as production control data. The ability of the computer to link such diverse information is the key to maintaining configuration control during the course of the design and construction. The ease with which formatted manufacturing data (both N.C. fabrication and installation) can be extracted enables the preparation of detailed packages containing the desired geometry as well as the associated material and sequencing data, thus assuring the producibility of the design. The SA'AR-5 design is CAD/CAM's state of the art in U.S. shipbuilding.
This paper discusses software pipelining for a new class of architectures that we call transport-triggered. These architectures reduce the interconnection requirements between function units. They also exhibit code sc...
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作者:
Corporal, H.Delft University of Technology
Faculty of Electrical Engineering Section Computer Architecture and Digital Mekelweg 4 P.O. Box 5031 Delft2600 Netherlands
Realtime behaviour is normally associated with maximal response time in worst case situations. The author introduces a somewhat different notion of realtime behaviour, called realtime performance, which is based on an...
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It is a well known fact that full custom designed computerarchitectures can achieve much higher performance for specific applications than general purpose computers. This performance has to be paid for: a long design...
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作者:
ZITZMAN, LHFALATKO, SMPAPACH, JLDr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group
Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department
Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department
Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin
This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis comp...
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This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computerarchitecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computerarchitecture to a general architecture for the future. The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st
Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or...
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ISBN:
(纸本)0897913000
Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion
Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, f...
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Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs;especially in the case of low-volume productions. The flexibility of horizontal...
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