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检索条件"机构=Computer Architecture and Technology Section"
48 条 记 录,以下是31-40 订阅
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COMPARING SOFTWARE PIPELINING FOR AN OPERATION-TRIGGERED AND A TRANSPORT-TRIGGERED architecture  4th
COMPARING SOFTWARE PIPELINING FOR AN OPERATION-TRIGGERED AND...
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4TH INTERNATIONAL WORKSHOP ON COMPILER CONSTRUCTION ( CC 92 )
作者: HOOGERBRUGGE, J CORPORAAL, H Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems Netherlands
This paper reports the results of a comparison between a new class of architectures, called transport-triggered architectures, and traditional architectures, called operation-t~iggered architectures. It does this comp... 详细信息
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Use of CMOS technology in wave pipelining  5
Use of CMOS technology in wave pipelining
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5th International Conference on VLSI Design, ICVD 1992
作者: Klass, F. Mulder, J.M. Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology Netherlands
Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. This is achieved by clocking the system faster than the propagatio... 详细信息
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CAD CAM GOES TO SEA - THE SAAR-5 DESIGN AND CONSTRUCTION
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NAVAL ENGINEERS JOURNAL 1992年 第3期104卷 148-155页
作者: LINDGREN, JR SOLITARIO, WA MOORE, AP STREIFF, MA John R. Lindgren Jr:. is vice president for engineering at Ingalls Shipbuilding Inc. a Division of Litton Industries in Pascagoula Miss. He joined Ingalls in 1958 and has held various positions in the Engineering Division and participated in the design of numerous merchant ships drill rigs submarines and surface combatants and auxiliary support ships. Mr. Lindgren is a 1958 graduate of the University of Southwest Louisiana. His degree is in mechanical engineering and he is also a licensed professional engineer. William A. Solitario:is the director of advanced technology at Ingalls Shipbuilding Inc. in Pascagoula Miss. He received his B.S. degree in chemical engineering from the City University of New York and has 28 years experience in marine engineering and design. His current responsibilities include the direction of Ingalls' IRAD programs and several Navy-funded R&D programs to improve ship's performance and reduce ship's operating costs. He is a member of the Society of Naval Architects and Marine Engineers and past chairman of the Gulf Section East Area. Arnold P. Moore:is the director design engineering at Ingalls Shipbuilding where he is responsible for all new construction design and engineering activities. Prior to promotion to his current position Mr. Moore served as chief naval architect at Ingalls. He has 24 years experience in ship design construction and repair. Mr. Moore holds the professional degree of ocean engineer as well as a master's degree in naval architecture and marine engineering from MIT. He also earned a bachelor's degree in naval science from the U.S. Naval Academy and is a registered professional engineer. Mr. Moore served as an engineering duty officer in the U.S. Navy and is currently a captain in the Naval Reserve. He is a past chairman of the Gulf Section of the Society of Naval Architects and Marine Engineers and a member of the American Society of Naval Engineers and Sigma Xi. Michel A. Streiff:is the manager of CAD/CAM applications at Ingalls Shipbuilding Inc. His
The SA'AR-5 Corvette Program is the first major warship construction to be entirely accomplished using a 3-dimensional, interference checked computer based design. This paper discusses the organization and approac... 详细信息
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Software pipelining for transport-triggered architectures  24
Software pipelining for transport-triggered architectures
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Proceedings of the 24th International Symposium on Microarchitecture - MICRO 24
作者: Hoogerbrugge, Jan Corporaal, Henk Mulder, Hans Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems
This paper discusses software pipelining for a new class of architectures that we call transport-triggered. These architectures reduce the interconnection requirements between function units. They also exhibit code sc... 详细信息
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Real realtime performance of heap management systems, using incremental copying collectors  24
Real realtime performance of heap management systems, using ...
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24th Annual Hawaii International Conference on System Sciences, HICSS 1991
作者: Corporal, H. Delft University of Technology Faculty of Electrical Engineering Section Computer Architecture and Digital Mekelweg 4 P.O. Box 5031 Delft2600 Netherlands
Realtime behaviour is normally associated with maximal response time in worst case situations. The author introduces a somewhat different notion of realtime behaviour, called realtime performance, which is based on an... 详细信息
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A scalable VLSI MIMD routing cell  6
A scalable VLSI MIMD routing cell
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6th Distributed Memory Computing Conference, DMCC 1991
作者: Corporaal, H. Oik, J.G.E. Delft University of Technology Faculty of Electrical Engineering Section Computer Architecture and Digital Systems Mekelweg 4 P.O. Box 5031 GA Delft2600 Netherlands
It is a well known fact that full custom designed computer architectures can achieve much higher performance for specific applications than general purpose computers. This performance has to be paid for: a long design... 详细信息
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computer-SYSTEM architecture CONCEPTS FOR FUTURE COMBAT SYSTEMS
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NAVAL ENGINEERS JOURNAL 1990年 第3期102卷 43-62页
作者: ZITZMAN, LH FALATKO, SM PAPACH, JL Dr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin
This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis comp... 详细信息
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Data buffering: run-time versus compile-time support
Data buffering: run-time versus compile-time support
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Third International Conference on Architectural Support for Programming Languages and Operating Systems Architectural Support for Programming Languages and Operating Systems
作者: Mulder, Hans Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology PO Box 5031 2600 AG Delft The Netherlands
Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or... 详细信息
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A flexible VLSI core for an adaptable architecture  22
A flexible VLSI core for an adaptable architecture
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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989
作者: Mulder, Hans Stravers, Paul Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands
Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, f... 详细信息
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Cost-effective design of application specific VLIW processors using the SCARCE framework  22
Cost-effective design of application specific VLIW processor...
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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989
作者: Mulder, Hans Portier, Robert J. Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands
Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs;especially in the case of low-volume productions. The flexibility of horizontal... 详细信息
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