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OpenPro: A Dynamic Profiling Tool Set for Exploring Thread-Level Speculation Parallelism

OpenPro: A Dynamic Profiling Tool Set for Exploring Thread-L...

引用

International Conference on computer and Electrical Engineering, ICCEE

作者： Yaobin Wang Hong An Bo Liang Li Wang Rui Guo Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Thread-level speculative (TLS) execution can facilitate automatic parallelization of programs that exhibit complicated memory access patterns, which make complete compile-time dependence analysis either impossible or extremely complicated. The decision on where to speculate can make a large difference in the resulting performance. Up to now, we still lack of appropriate dynamic profiling tool used to find and effectively exploit TLS parallelism. In this paper, we proposed a criterion for selecting the region to be speculatively executed and introduce a dynamic profiling tool set "OpenPro" which can be used to explore TLS parallelism for various applications in depth. The OpenPro can be used to analyze the key factors on TLS parallelism, such as inter-thread data dependence, inter-thread control-flow misprediction and inter-thread load imbalance, and to show the potential speedup to evaluate whether a given application or parts of it are suitable for TLS technology. By profiling the SPEC CPU2000 integer benchmark suite, we found that the TLS technology is not suitable for the traditional desktop applications.

关键词： Parallel processing Yarn Concurrent computing Runtime computer science Laboratories computer architecture Pattern analysis Delay Data analysis

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Round-robin based scheduling algorithms for FIFO IQ switch

Round-robin based scheduling algorithms for FIFO IQ switch

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IEEE International Conference on Networking, Sensing and Control

作者： Xiao-jing Zhu Hong-bo Zeng Kun Huang Ge Zhang Department of Computer Science and Technology University of Science and Technology China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of network on chip, which are called rr-path, rr-dist and rr-al respectively, rr-path schedules the NoC traffic according to the distance between the source node and the destination node, and rr-dist schedules the NoC traffic according to the distance between the current and the destination nodes, and rr-al schedules the NoC traffic according to the difference between the arrival and the left flits numbers of every ports. We implement these algorithms in a network simulator, and analyze their performance using hotspot and uniform traffic patterns. Compared to round-robin scheduling algorithm, all of the new algorithms can reduce the max communication latency. In most cases, they can also reduce the average communication latency. Consequently, these new algorithms can improve the performance of multiprocessor systems.

关键词： Scheduling algorithm Network-on-a-chip Telecommunication traffic Traffic control Switches Round robin Processor scheduling Delay computer networks High performance computing

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Performance-aware speculation control using wrong path usefulness prediction

Performance-aware speculation control using wrong path usefu...

引用

IEEE Symposium on High-Performance computer architecture

作者： Chang Joo Lee Hyesoon Kim Onur Mutlu Yale N. Patt Department of Electrical and Computer Engineering University of Texas Austin USA School of Computer Science Georgia Institute of Technology Computer Architecture Group Microsoft Research

ISBN: (纸本)9781424420704

Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrong-path (i.e. mis-speculated) instructions. These schemes assume that all wrong-path instructions are useless for processor performance and try to eliminate the execution of all wrong-path instructions. However, wrong-path memory references can be useful for performance by providing prefetching benefits for later correct-path operations. Therefore, eliminating wrong-path instructions without considering the usefulness of wrong-path execution can significantly reduce performance as well as increase overall energy consumption. This paper proposes a comprehensive, low-cost speculation control mechanism that takes into account the usefulness of wrong-path execution, while effectively reducing the energy consumption due to useless wrong-path instructions. One component of the mechanism is a simple, novel wrong-path usefulness predictor (WPUP) that can accurately predict whether or not wrong-path execution will be beneficial for performance. The other component is a novel branch-count based fetch gating scheme that requires very little hardware cost to detect if the processor is on the wrong path. The key idea of our speculation control mechanism is to gate the processor pipeline only if (1) the number of outstanding branches is above a dynamically-determined threshold and (2) the WPUP predicts that wrong-path execution will not be beneficial for performance. Our results show that our proposal eliminates most of the performance loss incurred by fetch gating mechanisms that assume wrong-path execution is useless, thereby both improving performance and reducing energy consumption while requiring very little (51- byte) hardware cost.

关键词： Prefetching Pipelines Hardware Engines Logic gates Energy consumption Benchmark testing

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A novel histogram definition for fuzzy color spaces

A novel histogram definition for fuzzy color spaces

引用

IEEE International Conference on Fuzzy Systems (FUZZ-IEEE)

作者： J. Chamorro-Martinez D. Sanchez J.M. Soto-Hidalgo Department of Computer Science and Artificial Intelligence University of Granada Spain Department of Computer Architecture Electronics and Electronic Technology University of Córdoba Spain

In this paper we introduce fuzzy naturals-based histograms on fuzzy color spaces. In our approach, histograms are fuzzy probability distributions on a fuzzy color space, where the fuzzy probability is calculated as the quotient between a fuzzy natural number and the number of pixels in the image, the former being a fuzzy (non-scalar) cardinality of a fuzzy set. This approach to histograms avoids the well-known disadvantages of the ordinary sigma-count as an estimation of the probability. We illustrate the potential application of the proposal by applying it to the problem of dominant color selection.

关键词： Image color analysis Histograms Color Pixel Probability distribution Proposals Approximation methods

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Improving data availability for a cluster file system through replication

Improving data availability for a cluster file system throug...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jin Xiong Jianyu Li Rongfeng Tang Yiming Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Electrical & Computer Engineering and Computer Science University of Cincinnati USA

Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how to efficiently guarantee replicas consistency under concurrent conflict mutations remains a challenge. Moreover, how to quickly recover replica consistency from a storage server crash or storage device failure is also a tough problem. In this paper, we present a replication-based data availability mechanism designed for a large-scale cluster file system prototype named LionFS. Unlike other replicated storage systems that serialize replica updates, LionFS introduces a relaxed consistency model to enable concurrent updating all replicas for a mutation operation, greatly reducing the latency of operations. LionFS ensures replica consistency if applications use file locks to synchronize the concurrent conflict mutations. Another novelty of this mechanism is its light-weight log, which only records failed mutations and imposes no overhead on failure-free execution and low overhead when some storage devices are unavailable. Furthermore, recovery of replica consistency needs not stop the file system services and running applications. Performance evaluation shows that our solution achieves 50-70% higher write performance than serial replica updates. The logging overhead is shown to be low, and the recovery time is proportional to the amount of data written during the failure.

关键词： File systems Genetic mutations computer crashes Large-scale systems Availability Peer to peer computing Delay Bandwidth Laboratories computer architecture

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Multi-Hop Synchronization at the Application Layer of Wireless and Satellite Networks

Multi-Hop Synchronization at the Application Layer of Wirele...

引用

IEEE GLOBECOM 2008 - 2008 IEEE Global Telecommunications Conference

作者： A. Marco R. Casas J. L. Sevillano V. Coarasa J. L. Falco M. S. Obaidat Tecnodiscap group University of Zaragoza Spain Department of Computer Architecture and Technology University of Sevilla Spain Computer Science Department Monmouth University NJ USA

Time synchronization is a key issue in wireless and satellite networks; time-stamping collected data, tasks scheduling or efficient communications are just some applications. From all the existing techniques to achieve synchronization, those that work at the MAC layer and can precisely timestamp sync messages are the most accurate. However, working with standard protocols, usually prevents the user from accessing lower layers and consequently reduces accuracy. Receiver-receiver schema improves time-stamping performance because it eliminates the biggest non-deterministic error at the sender side; the medium access time. Nevertheless, utilization of these methods in multi- hop networks usually requires an extra amount of traffic. In this paper we present a method which allows accurate synchronization of large multi-hop networks such as satellite networks working at the application layer while keeping the message exchange to the minimum. Through an exhaustive experimentation, we show the protocol's performance and analyze the factors that influence synchronization accuracy the most.

关键词： Spread spectrum communication Frequency synchronization Satellite broadcasting Clocks Low earth orbit satellites Application software Performance analysis Time division multiple access Protocols Synthetic aperture radar interferometry

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AER filtering using GLIDER: VHDL cellular automata description

AER filtering using GLIDER: VHDL cellular automata descripti...

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： A. Linares-Barranco J.L. Sevillano M. S. Obaidat N. Ferrando J. Cerda D. Cascado G. Jimenez A. Civit Department of Computer Architecture and Technology University of Seville Spain Computer Science Department Monmouth University NJ USA Department of Electronic Engineering Technical University of Valencia Spain

Cellular automata (CA) is a bio-inspired processing model for problem solving, initially proposed by Von Neumann. This approach modularizes the processing by dividing the solution into synchronous cells that change their states at the same time in order to get the solution. The communication between them is crucial to achieve the correct solution. On the other hand, the address-event-representation (AER) is a neuromorphic communication protocol for transferring asynchronous events between VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, which makes it possible to develop complex, multilayer, multichip neuromorphic systems. This paper presents the fusion of both bio-inspired solutions for implementing a vision filter based on 3times3 convolutions. The GLIDER software tool for developing CA has been used to implement the filter in VHDL and synthesize it into the Spartan II 200 of the USB-AER.

关键词： Filtering Filters Neuromorphics Problem-solving Protocols Very large scale integration Biosensors Sensor systems Retina Nonhomogeneous media

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Error Restricted Piecewise Linear Representation of Time Series Based on Special Points

Error Restricted Piecewise Linear Representation of Time Ser...

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World Congress on Intelligent Control and Automation (WCICA)

作者： Pengtao Jia Huacan He Tao Sun School of Computer Science Northwestern Polytechnical University Xi'an China Department of Computer Science Xi''an University of Science and Technology Xi'an China School of Architecture and Civil Engineering Xi''an University of Science and Technology Xi'an China

Time series composed of a series of data observed according to time sequence. There are large numbers of time series in the field of automatic control. Usually time series data is massive. Sometimes, it is inefficient or impractical to mine the original time series data directly. So time series should be represented on higher level. Piecewise Linear Representation is perhaps the most frequently used representation with lower dimensions of index structure and the faster speed of calculation. But PLR needs a parameter k given by users and to make certain k is not easy for the users. We put forward an algorithm of error restricted piecewise linear representation based on special points that can give the number of fitting lines automatically according to a given error e. And it has lower time complexity than other error restricted algorithm, such as sliding windows, Bottom-Up, Top-Down. According to experiments our algorithm leads to less fitting error and better performance than other algorithms. So it would be more efficient in the real application of control fields.

关键词： Time series analysis Approximation algorithms Fitting Approximation methods Complexity theory Piecewise linear approximation Algorithm design and analysis

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An Approach to Addressing Entity Model Variability within Software Product Lines

An Approach to Addressing Entity Model Variability within So...

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International Conference on Software Engineering Advances (ICSEA)

作者： Joerg Bartholdt Roy Oberhauser Andreas Rytina Corporate Technology Architecture Siemens AG Munich Germany Computer Science Department Aalen University Aalen Germany

Software product line (SPL) engineering is one approach for addressing customization and variability for products. However, current approaches and research, while often addressing feature modeling and component variability, insufficiently address difficulties and additional complexity with respect to entity model variability, which negatively impacts various software qualities, such as correctness, reusability, maintainability, testability, and evolvability. This paper presents a solution approach with an integrated mechanism providing a consistent view to capture data variability in entity models, while hiding and decoupling components from superfluous data elements via adapter generation. An eHealth SPL case study is presented supporting adapter generation with differential entity conversion. The results show that with this approach, entity model variability can be effectively addressed and desirable software qualities preserved.

关键词： computer architecture Software quality Software engineering computer science Maintenance engineering Software testing Software systems Application software Automation Scalability

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COMPOSITION OF CONCEPT LATTICES

COMPOSITION OF CONCEPT LATTICES

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2008 International Conference on Machine Learning and Cybernetics(2008机器学习与控制论国际会议)

作者： JIAN-JUN QI LING WEI YUN-BO BAI School of Computer Science & Technology Xidian University Xi'an 710071China Department of Mathematics Northwest University Xi'an 710069China Section of Computer Science Xi'an Politics Institute Xi'an 710068China

The theory of concept lattices is an efficient tool for knowledge discovery. The purpose of this paper is to discuss the composed lattice of two concept lattices with the same object set. We first define a pair of Galois connection between two posets obtained from two formal contexts, and discuss the properties of the Galois connection. Then, we define the composition of two concept lattices that have the same object set, and prove that it is a complete lattice. Finally, we discuss the relationship between the composed lattice and the concept lattice of the composed context, and prove that the composed lattice is a subset of the concept lattice of the composed context. Numerical example is employed to substantiate the theoretical arguments.

关键词： Formal Contezt Concept Lattice Galois Connection Composition

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