A general problem in model selection is to obtain the right parameters that make a model fit observed data. For a multilayer perceptron (MLP) trained with backpropagation (BP), this means finding the right hidden laye...
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A general problem in model selection is to obtain the right parameters that make a model fit observed data. For a multilayer perceptron (MLP) trained with backpropagation (BP), this means finding the right hidden layer size, appropriate initial weights and learning parameters. The paper proposes a method (G-Prop-II) that attempts to solve that problem by combining a genetic algorithm (GA) and BP to train MLPs with a single hidden layer. The GA selects the initial weights and the learning rate of the network, and changes the number of neurons in the hidden layer through the application of specific genetic operators. G-Prop-II combines the advantages of the global search performed by the GA over the MLP parameter space and the local search of the BP algorithm. The application of the G-Prop-II algorithm to several real world and benchmark problems shows that MLPs evolved using G-Prop-II are smaller and achieve a higher level of generalization than other perceptron training algorithms, such as QuickPropagation or RPROP, and other evolutive algorithms, such as G-LVQ. It also shows some improvement over previous versions of the algorithm.
This paper deals with the problem of finding a suitable framework for designing computer simulations that could help us determine the minimal requirements (both material and organizational) for the origin of the first...
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The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the contex...
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The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. Such a study is interesting as the dynamic instruction ordering and register renaming support mechanisms in out-of-order issue processors are similar in spirit to what the complex register allocation and instruction scheduling techniques do at compile-time. We evaluated four existing techniques, namely postpass scheduling, prepass scheduling, parallel interference graph, and integrated prepass scheduling methods. Our initial experimental results reveal that for o-o-o issue processors the focus should be on reducing the register pressure/spill code than exposing the parallelism at compiling time.
Endocardial border detection is a crucial step for the quantitative analysis of overall and regional left ventricular function from echocardiographic images. Echocardiographic contrast agents with transpulmonary passa...
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Endocardial border detection is a crucial step for the quantitative analysis of overall and regional left ventricular function from echocardiographic images. Echocardiographic contrast agents with transpulmonary passage are being used increasingly in clinical practice for left ventricular cavity opacification. We investigate the feasibility of using pulse coupled neural networks to identify, the left ventricular endocardial border in contrast-enhanced echocardiographic cineloops.
This paper presents the architecture of a router designed to efficiently support traffic generated by multimedia applications. The router is targeted for use in clusters and LANs rather than in WANs, the latter being ...
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This paper presents the architecture of a router designed to efficiently support traffic generated by multimedia applications. The router is targeted for use in clusters and LANs rather than in WANs, the latter being served by communication substrates such as ATM. The distinguishing features of the proposed router architecture are the use of small fixed-size buffers, a large number of virtual channels, link-level virtual channel flow control, support for dynamic modification of connection bandwidth and priorities, and coordinated scheduling of connections across all output channels. The paper begins with a discussion of the design choices and architectural trade-offs made in the current MultiMedia Router (MMR) project. The performance evaluation section presents some preliminary results of the coordinated scheduling of constant bit rate (CBR) traffic streams.
Presents a technique for automatically computing stroke volume from 2-D color flow echocardiographic cineloops of the left ventricular outflow tract (LVOT). By utilizing the anatomical and blood velocity information i...
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Presents a technique for automatically computing stroke volume from 2-D color flow echocardiographic cineloops of the left ventricular outflow tract (LVOT). By utilizing the anatomical and blood velocity information in the color flow image, the measurement technique eliminated many of the technical obstacles and assumptions in existing methods. This technique determines the blood flow vector, LVOT conduit border, and ejection period without human guidance, and the stroke volume is computed automatically. The resulting automated technique improves measurement accuracy and speed and only requires one data set (a color flow cineloop).
All-or-nothing property is a new encryption mode proposed by Rivest and has the property that one must decrypt the entire ciphertext to determine any plaintext block. In this paper, we propose a hash function with all...
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Standard user-level networking architecture such as Virtual Interface (VI) architecture enables distributed applications to perform low overhead communication over System Area Networks (SANs). This paper describes how...
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Emerging design problems are prompting the use of code motion and speculation in high-level synthesis to shorten schedules and meet tight time-constraints. Unfortunately, they may increase the number of states to an e...
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Emerging design problems are prompting the use of code motion and speculation in high-level synthesis to shorten schedules and meet tight time-constraints. Unfortunately, they may increase the number of states to an extent not always affordable for embedded systems. We propose a new technique that not only leads to less states, but also speeds up scheduling. Equivalent states are predicted and merged while building the finite state machine. Experiments indicate that flexible code motions can be used, since our technique restrains state expansion.
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