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检索条件"机构=Computer Architecture and VLSI Systems Laboratory"
8 条 记 录,以下是1-10 订阅
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Multi-FPGA Evaluation Platform for Disaggregated Computing
Multi-FPGA Evaluation Platform for Disaggregated Computing
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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
作者: Dimitris Theodoropoulos Nikolaos Alachiotis Dionisios Pnevmatikatos Computer Architecture and VLSI Systems Laboratory Institute of Computer Science Foundation for Research and Technology - Hellas (FORTH)
We present a versatile FPGA-based evaluation platform for exploring alternative execution strategies on disaggregated environments for applications, considering different processing block types: compute cores, memory,... 详细信息
来源: 评论
Efficient runtime support for embedded MPSoCs
Efficient runtime support for embedded MPSoCs
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International Conference on Embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)
作者: Dimitris Theodoropoulos Polyvios Pratikakis Dionisios Pnevmatikatos Computer Architecture and VLSI Systems Laboratory Institute of Computer Science Foundation for Research and Technology-Hellas Crete Greece
Recently, many software runtime systems have been proposed that allow developers to efficiently map applications to contemporary consumer electronic devices and high-performance academic processing platforms. Most of ... 详细信息
来源: 评论
FPGA-based architecture of 3-D HWT using distributed arithmetic (DA)
FPGA-based architecture of 3-D HWT using distributed arithme...
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IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES)
作者: Azlan Muharam Afandi Ahmad VLSI Architecture and Systems Design Research Laboratory Universiti Tun Hussein Onn Malaysia (UTHM) Beg Berkunci Johor Department of Computer Engineering UTHM
This paper describes the design and implementation of three-dimensional (3-D) Haar with transpose-based computation and distributed arithmetic (DA). As a results of the separately property of the multi-dimensional Haa... 详细信息
来源: 评论
Affine-NoC: Multi-ring NoCs exploiting long physical links
Affine-NoC: Multi-ring NoCs exploiting long physical links
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International Workshop on Network on Chip architectures, NoCArc
作者: Enrique Vallejo Evangelos Mageiropoulos Nikolaos Chrysos Manolis G.H. Katevenis Computer Science Dept. Universidad de Cantabria Spain Santander Spain Computer Architecture and VLSI Systems (CARV) Laboratory Foundation for Research and Technology – Hellas (FORTH) Heraklion Greece
Routerless multi-ring proposals are low-cost NoCs that employ multiple independent rings, avoiding any crossbars or arbitration mechanisms. Their complexity lies on the selection of the set of rings to connect all the... 详细信息
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Temperature-aware software-based self-testing for delay faults  15
Temperature-aware software-based self-testing for delay faul...
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Design, Automation and Test in Europe Conference and Exhibition
作者: Ying Zhang Zebo Peng Jianhui Jiang Huawei Li Masamro Fujita School of Software Engineering Tongji University China Embedded Systems Lab Linköping University Sweden State Key Laboratory of Computer Architecture Chinese Academy of Sciences China VLSI Design and Education Center University of Tokyo Japan
Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don't address this problem properly. In this paper, a tem... 详细信息
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Distributed arithmetic architecture of Discrete Wavelet Transform (DWT) with hybrid method
Distributed arithmetic architecture of Discrete Wavelet Tran...
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IEEE International Conference on Electronics, Circuits and systems (ICECS)
作者: Noor Huda Ja'afar Afandi Ahmad Abbes Amira VLSI Architecture and Systems Design Research Laboratory Universiti Tun Hussein Onn Malaysia Batu Pahat Johor MALAYSIA Department of Computer Engineering Universiti Tun Hussein Onn Malaysia Batu Pahat Johor MALAYSIA School of Computing University of the West of Scotland Paisley United Kingdom
This paper presents the design and implementation of distributed arithmetic (DA) architectures of three-dimensional (3-D) Discrete Wavelet Transform (DWT) with hybrid method for medical image compression. Due to the s... 详细信息
来源: 评论
Rapid prototyping of neonatal jaundice detector using skin optics theory
Rapid prototyping of neonatal jaundice detector using skin o...
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IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES)
作者: Zulfadhli Osman Afandi Ahmad Azlan Muharam Bioelectronics and Instrumentation Research Laboratory (BioEI) Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat Johor Malaysia Department of Computer Engineering Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat Johor Malaysia VLSI Architecture and Systems Design Research Laboratory Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat Johor
When newborns present with jaundice, various clinical assessment need to be executed including evaluation of the history, physical examination, and assessment of severity of jaundice. This project concerns with the qu... 详细信息
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The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack
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ACM Transactions on Reconfigurable Technology and systems 1000年
作者: Manolis Ploumidis Fabien Chaix Nikolaos Chrysos Marios Assiminakis Nikolaos Kallimanis Nikolaos Kossifidis Mickael Nikoloudakis Nikolaos Dimou Michalis Gianioudis George Ieronymakis Aggelos Ioannou George Kalokerinos Pantelis Xirouchakis Astrinos Damianakis Mickael Ligerakis Theocharis Vavouris Manolis Katevenis Vassilis Papaefstathiou Manolis Marazakis Iakovos Mavroidis Computer Architecture and VLSI Systems (CARV) Laboratory Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH) Greece
We present and evaluate the ExaNeSt Prototype, which compactly packages 128 Xilinx ZU9EG MPSoCs, 2 TBytes of DRAM, and 8 TBytes of SSD into a liquid-cooled rack, using a custom interconnection hardware based on 10 Gbp... 详细信息
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