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International Workshop on Network on Chip architectures, NoCArc

作者： Enrique Vallejo Evangelos Mageiropoulos Nikolaos Chrysos Manolis G.H. Katevenis Computer Science Dept. Universidad de Cantabria Spain Santander Spain Computer Architecture and VLSI Systems (CARV) Laboratory Foundation for Research and Technology – Hellas (FORTH) Heraklion Greece

ISBN: (数字)9798331506421

ISBN: (纸本)9798331506438

Routerless multi-ring proposals are low-cost NoCs that employ multiple independent rings, avoiding any crossbars or arbitration mechanisms. Their complexity lies on the selection of the set of rings to connect all the nodes. Previous proposals result in unbalanced designs with high hop *** work introduces Affine-NoC, a balanced routerless NoC based on a novel arrangement of rings derived from the Affine Plane. Affine-NoC exploits express channels to connect distant processing elements, allowing for a completely balanced layout of the set of rings and a reduction in average distance and diameter without sacrificing bisection *** shows that Affine-NoC presents a balanced design with a low number of rings per node and reduced complexity, similar cost to previous proposals in terms of aggregated link length, while it simplifies the multiplex units and reduces the hop count. Simulation results show that Affine-NoC reduces hop count and average latency by 76% and 20.5% respectively compared to previous designs, it reduces deflections by 27% and avoids unfairness, making it a feasible alternative for multi-ring routerless NoCs.

关键词： Multiplexing Network topology Flow production systems Simulation Layout computer architecture Complexity theory Topology Proposals Logic

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Multi-FPGA Evaluation Platform for Disaggregated Computing

Multi-FPGA Evaluation Platform for Disaggregated Computing

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Dimitris Theodoropoulos Nikolaos Alachiotis Dionisios Pnevmatikatos Computer Architecture and VLSI Systems Laboratory Institute of Computer Science Foundation for Research and Technology - Hellas (FORTH)

We present a versatile FPGA-based evaluation platform for exploring alternative execution strategies on disaggregated environments for applications, considering different processing block types: compute cores, memory, and accelerators. Developers can interconnect different blocks types in order to create optimal configurations. A user-level software library allows quick mapping of applications on real hardware. We have implemented a fully working prototype using three ZC706 FPGA boards, and evaluated different software / hardware configurations of a matrix multiplication benchmark.

关键词： computer architecture Hardware Software Acceleration Prototypes Benchmark testing Resource management

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Temperature-aware software-based self-testing for delay faults 15

Temperature-aware software-based self-testing for delay faul...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ying Zhang Zebo Peng Jianhui Jiang Huawei Li Masamro Fujita School of Software Engineering Tongji University China Embedded Systems Lab Linköping University Sweden State Key Laboratory of Computer Architecture Chinese Academy of Sciences China VLSI Design and Education Center University of Tokyo Japan

ISBN: (纸本)9783981537048

Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don't address this problem properly. In this paper, a temperature-aware software-based self-testing (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates high-quality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.

关键词： Delays Program processors Temperature distribution Power dissipation Circuit faults Schedules

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FPGA-based architecture of 3-D HWT using distributed arithmetic (DA)

FPGA-based architecture of 3-D HWT using distributed arithme...

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IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES)

作者： Azlan Muharam Afandi Ahmad VLSI Architecture and Systems Design Research Laboratory Universiti Tun Hussein Onn Malaysia (UTHM) Beg Berkunci Johor Department of Computer Engineering UTHM

This paper describes the design and implementation of three-dimensional (3-D) Haar with transpose-based computation and distributed arithmetic (DA). As a results of the separately property of the multi-dimensional Haar wavelet transform (HWT), the proposed architecture has been implemented using a cascade of three N-point one-dimensional (1-D) Haar and two transpose memories for a 3-D volume of N × N × N, suitable for 3-D medical image compression. The 3-D HWT architecture were implemented on SubRIO-9632 board National Instrument. Experimental result and analysis of area, power consumption and maximum frequency are discussed in this paper.

关键词： Field programmable gate arrays Biomedical imaging Image coding Table lookup Discrete wavelet transforms

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Rapid prototyping of neonatal jaundice detector using skin optics theory

Rapid prototyping of neonatal jaundice detector using skin o...

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IEEE EMBS Conference on Biomedical Engineering and Sciences (IECBES)

作者： Zulfadhli Osman Afandi Ahmad Azlan Muharam Bioelectronics and Instrumentation Research Laboratory (BioEI) Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat Johor Malaysia Department of Computer Engineering Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat Johor Malaysia VLSI Architecture and Systems Design Research Laboratory Universiti Tun Hussein Onn Malaysia (UTHM) Batu Pahat Johor

When newborns present with jaundice, various clinical assessment need to be executed including evaluation of the history, physical examination, and assessment of severity of jaundice. This project concerns with the quantification of neonatal jaundice level using Simulink model-based design. It is important to address that the proposed method is non-invasive, hence suitable for infants. In this project, the concentration level of bilirubin in dermis layer of skin has been detected using skin optic theory with light emitting diode (LED) and photodiode as a detector. To evaluate the proposed system, a mock skin soaking is used to replace the real infant's skin. At the system level, Arduino Uno has been used as a hardware platform, whilst MATLAB and Simulink have been fully utilised to implement the system's architecture. An evaluation of the proposed systems reveals its capability to detect, process and display real-time results with three (3) levels of jaundice, including normal, mild and critical.

关键词： Skin Pediatrics Photodiodes Light emitting diodes Conferences Optics Blood

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Efficient runtime support for embedded MPSoCs

Efficient runtime support for embedded MPSoCs

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International Conference on Embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Dimitris Theodoropoulos Polyvios Pratikakis Dionisios Pnevmatikatos Computer Architecture and VLSI Systems Laboratory Institute of Computer Science Foundation for Research and Technology-Hellas Crete Greece

ISBN: (纸本)9781479901043

Recently, many software runtime systems have been proposed that allow developers to efficiently map applications to contemporary consumer electronic devices and high-performance academic processing platforms. Most of these runtime systems employ advanced scheduling techniques for automatic task assignment to all available processing elements. However, they focus on a particular environment and architecture, and it is not easy to port them to reconfigurable embedded MPSoCs. As a consequence, in the embedded community, researchers implement hardwired application-specific task schedulers, which can not be used by other embedded MPSoCs. To address this problem, in this paper we propose a lightweight runtime software framework for reconfigurable shared-memory MPSoCs, that integrate a master embedded processor connected to slave cores. Similarly to many of the aforementioned advanced runtime systems, we adopt a task-based programming model that uses simple, pragma-based annotations of the application software, in order to dynamically resolve task dependencies. Our runtime system supports heterogeneity in the hardware resources, and is also low-overhead to account for possible limitations in their processing capabilities and available on-chip memory. To evaluate our proposal, we have prototyped an MPSoC with seven slaves to a Xilinx ML605 FPGA board. We run three micro-benchmarks that achieve a performance speedup of 3.8x, 7x and 5.8x, and energy consumption of 27%, 14% and 18% respectively, compared to a single-core baseline system with no runtime support.

关键词： Runtime Software Hardware Real-time systems Field programmable gate arrays Processor scheduling Programming

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Distributed arithmetic architecture of Discrete Wavelet Transform (DWT) with hybrid method

Distributed arithmetic architecture of Discrete Wavelet Tran...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Noor Huda Ja'afar Afandi Ahmad Abbes Amira VLSI Architecture and Systems Design Research Laboratory Universiti Tun Hussein Onn Malaysia Batu Pahat Johor MALAYSIA Department of Computer Engineering Universiti Tun Hussein Onn Malaysia Batu Pahat Johor MALAYSIA School of Computing University of the West of Scotland Paisley United Kingdom

This paper presents the design and implementation of distributed arithmetic (DA) architectures of three-dimensional (3-D) Discrete Wavelet Transform (DWT) with hybrid method for medical image compression. Due to the separability property of the multi-dimensional Haar and Daubechies, the proposed architecture has been implemented using a cascade of three N-point one-dimensional (1-D) Haar/Daubechies and two transpose memories for a 3-D volume of N×N×N, suitable for 3-D medical imaging applications. The architectures were synthesised using VHDL and G-code and implemented on field programmable gate array (FPGA) single board RIO (sbRIO-9632) with Spartan-3 (XC3S2000). Experimental results and an analysis of the area, power consumption, maximum frequency, latency, throughput as well as the subjective test are discussed in this paper.

关键词： Discrete wavelet transforms Table lookup Biomedical imaging Field programmable gate arrays

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The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack

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ACM Transactions on Reconfigurable Technology and systems 1000年

作者： Manolis Ploumidis Fabien Chaix Nikolaos Chrysos Marios Assiminakis Nikolaos Kallimanis Nikolaos Kossifidis Mickael Nikoloudakis Nikolaos Dimou Michalis Gianioudis George Ieronymakis Aggelos Ioannou George Kalokerinos Pantelis Xirouchakis Astrinos Damianakis Mickael Ligerakis Theocharis Vavouris Manolis Katevenis Vassilis Papaefstathiou Manolis Marazakis Iakovos Mavroidis Computer Architecture and VLSI Systems (CARV) Laboratory Institute of Computer Science (ICS) Foundation for Research and Technology – Hellas (FORTH) Greece

We present and evaluate the ExaNeSt Prototype, which compactly packages 128 Xilinx ZU9EG MPSoCs, 2 TBytes of DRAM, and 8 TBytes of SSD into a liquid-cooled rack, using a custom interconnection hardware based on 10 Gbps links. We developed this testbed in 2016-2019 in order to leverage the flexibility of FPGAs for experimenting with efficient hardware support for HPC communication among tens of thousands of processors and accelerators in the quest towards Exascale systems and beyond. In the years since then, we carefully studied this system, and we present our key design choices and insights resulting from our measurement and *** developed this testbed, from architecture to the PCBs and the runtime software, within the ExaNeSt project. It is fully operational in configurations with up to 8x4x4 MPSoC nodes. It achieves high density through tight board design, while also leveraging state-of-the-art liquid cooling technology. In this paper, we present a thorough architectural analysis, along with important aspects of our infrastructure development. Our custom interconnect includes a low-cost low-latency network interface, offering user-level, zero-copy RDMA, which we coupled with the ARMv8 processors in the MPSoCs. We further developed the corresponding runtimes that allow us to test real MPI applications on the large-scale *** evaluated our platform through MPI microbenchmarks, mini, and full MPI applications. Single hop, one way latency is \(1.3\) \(\mu\)s; approximately \(0.47\) \(\mu\)s out of these are attributed to network interface and the user-space library that exposes its functionality to the runtime. Latency over longer paths increases as expected, reaching \(2.55\) \(\mu\)s for a five-hop path. Bandwidth tests show that, for single hop, link utilization reaches \(82\%\) of the theoretical capacity. Microbenchmarks based on MPI collectives reveal that broadcast latency scales as expected when the number of participating ranks increases. We also

关键词： High-speed Network Low-latency High-density Codesign PGAS MPI Exascale

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