CMOS technology evolution enhances integrated circuits (ICs) performance characteristics at the cost of their increased susceptibility to radiation and thus to the occurrence of single-event upsets (SEUs) that may lea...
CMOS technology evolution enhances integrated circuits (ICs) performance characteristics at the cost of their increased susceptibility to radiation and thus to the occurrence of single-event upsets (SEUs) that may lead to soft errors generation. SEUs may affect multiple nodes in a circuit (multiple node upsets - MNUs). Fortunately, these disturbances do not cause permanent damage to the circuits. Various techniques have been proposed to deal with SEUs that concurrently affect one, two or three nodes. In this paper, we propose the design of a latch that offers tolerance up to the level of triple-node upsets (TNUs). This is achieved by using redundancy in the hardware which provides the ability to store a logic value in multiple nodes within the latch as well as by using multiple feedback paths which allow it to recover its correct state in the event of an SEU. Compared to other techniques dealing with the same problem, our proposed method provides faster recovery time (higher than 16.87%) after an SEU, and at the same time reduced power consumption and higher speed performance.
High-performance interconnects need congestion control to deal with traffic bursts. In this paper, we propose ACCurate, a congestion control protocol that assigns exact max-min fair rates to flows, without relying on ...
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ISBN:
(纸本)9781538648933
High-performance interconnects need congestion control to deal with traffic bursts. In this paper, we propose ACCurate, a congestion control protocol that assigns exact max-min fair rates to flows, without relying on costly per-flow state inside the network. ACCurate keeps the backlogs outside of the network, protects innocent flows, and promptly recovers the flows' rates after congestive episodes. Comparisons with TCP and PAUSE-only RDMA under datacenter-resembling workloads further show that ACCurate provides up to 10× faster flow completion times. ACCurate relies on simple hardware that can be readily implemented inside switches. In our implementation, the additional circuitry needed in a 16×16 switch occupies less than 2% of FPGA resources.
Delay defects under high temperature have been one of the most critical factors to affect the reliability of computersystems, and the current test methods don't address this problem properly. In this paper, a tem...
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ISBN:
(纸本)9783981537048
Delay defects under high temperature have been one of the most critical factors to affect the reliability of computersystems, and the current test methods don't address this problem properly. In this paper, a temperature-aware software-based self-testing (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates high-quality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.
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