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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： A. Pacholik J. Klockner M. Muller I. Gushchina W. Fengler Computer Architecture and Embedded Systems Group Ilmenau University of Technology Ilmenau Germany

The development of industrial control and measurement systems is often based on modular commercial off the-shelf hardware. Lately, for these platforms reconfigurable I/O modules with field-programmable gate arrays (FPGA) have gained significance, since they allow the implementation of data processing functionality very close to the data acquisition interfaces. However, algorithm complexity and floating-point support are limited by FGPA resources and design methods. This contribution presents an application specific configurable DSP soft core architecture built around a scalable double precision floating-point arithmetic/logic unit. The core can be seamlessly utilized as a functional component in Lab VIEW based FPGA designs. A small case study shows the performance of an example application implemented on the presented core in comparison to other embedded architectures.

关键词： Field programmable gate arrays computer architecture Registers Hardware Pipelines Algorithm design and analysis Program processors

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Systematic Construction of Deadlock-Free Routing for NoC Using Integer Linear Programming

Systematic Construction of Deadlock-Free Routing for NoC Usi...

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IEEE International Symposium on embedded Multicore Socs (MCSoC)

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

Network-on-Chip (NoC) presents a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). This work addresses critical challenges in NoC design, including routing construction, application mapping, and particularly the issue of deadlocks in the widely-used wormhole routing method. In this paper, an Integer Linear Programming (ILP) approach for deadlock-free routing is proposed, applicable to arbitrary network topologies. We systematically analyze deadlock-free routing construction for mesh and torus topologies under uniform random traffic and provide alternative solutions to turn models. In the context of application-specific NoCs, application mapping, and deadlock-free routing are integrated within a single ILP. Through evaluation with several benchmark applications, it is demonstrated that the ILP method consistently delivers optimal solutions and could obtain better results than various heuristic methods within an acceptable time. Fault tolerance is also explored and existing techniques are incorporated into the ILP approach. As an illustrative example, application mapping and a 1-link-fault-tolerant deadlock-free routing for the MP3 application on a mesh network is performed.

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Synergistic Floorplanning and Routing Topology Co-design for Application-Specific NoC Synthesis

Synergistic Floorplanning and Routing Topology Co-design for...

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IEEE International Symposium on embedded Multicore Socs (MCSoC)

作者： Shuang Liu Martin Radetzki Chair of Embedded Systems Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798331530471

ISBN: (纸本)9798331530488

Network-on-Chip (NoC) offers a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). NoCs can be designed with either regular or application-specific network topologies. While regular topologies are easy to design, they are not ideal for systems with heterogeneous processing elements (PEs) that vary in size. The design of application-specific NoCs, however, involves several interrelated problems that impact each other. This work addresses the challenges in the synthesis of application-specific NoCs by proposing an Integer Linear Programming (ILP) framework. This framework enables the co-design of major problems, including floorplanning, routing topology generation, routing path construction, and application mapping. Although the ILP framework can be applied to each problem individually or in a stepwise manner, the co-design of these interconnected problems allows synthesis steps to interact, enabling designers to explore the entire design space. Using this framework, we have analyzed various design configurations in the synthesis of application-specific NoCs.

关键词： Network topology Multicore processing Fault tolerant systems Network-on-chip System recovery Integer linear programming Routing Linear programming Topology Wire

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High level structural description of streaming applications

High level structural description of streaming applications

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International Conference on Field Programmable Logic and Applications

作者： Anja Niedermeier Jan Kuper Gerard J.M. Smit Faculty of Electrical Engineering Mathematics and Computer Science Computer Architecture Embedded Systems University of Twente Netherlands

The research has been motivated by the desire for a straightforward implementation of an application described as a dataflow graph on a multicore architecture. The design has been based on an already existing language that inherently has a notion of structure: the functional programming language Haskell. Haskell has been used both for embedding the grammar for proposed language as well as to describe streaming applications with the proposed language.

关键词： Production Kernel computer architecture Functional programming Grammar Syntactics Hardware

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A dataflow-inspired CGRA for streaming applications

A dataflow-inspired CGRA for streaming applications

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International Conference on Field Programmable Logic and Applications

作者： Anja Niedermeier Jan Kuper Gerard J.M. Smit Faculty of Electrical Engineering Mathematics and Computer Science Computer Architecture Embedded Systems University of Twente Netherlands

The herein presented research is motivated by the need for reconfigurable, flexible computing arrays targeted at streaming applications that contain a large degree of instruction-level parallelism. Such arrays are usually referred to as coarse-grained reconfigurable arrays (CGRAs). CGRAs are composed of small, reconfigurable cores that are interconnected to form a computing grid. Here, we present a complete CGRA, consisting of an architecture and a programming language. Both the architecture and the programming language are inspired by the principles found in dataflow.

关键词： computer architecture Programming Registers Program processors Parallel processing computer languages Vectors

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C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell

C?aSH: Structural Descriptions of Synchronous Hardware Using...

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Euromicro Symposium on Digital System Design

作者： Christiaan Baaij Matthijs Kooijman Jan Kuper Arjan Boeijink Marco Gerards Computer Architecture for Embedded Systems (CAES) Department of EEMCS University of Twente Enschede Netherlands

CλaSH is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. Polymorphism and higher-order functions provide a level of abstraction and generality that allow a circuit designer to describe circuits in a more natural way than possible with the language elements found in the traditional hardware description languages. Circuit descriptions can be translated to synthesizable VHDL using the prototype CλaSH compiler. As the circuit descriptions, simulation code, and test input are also valid Haskell, complete simulations can be done by a Haskell compiler or interpreter, allowing high-speed simulation and analysis.

关键词： Hardware Integrated circuit modeling Pattern matching Hardware design languages Multiplexing Prototypes Radiation detectors

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Designing a Control Application by Using a Specialized Multi-Core Soft Microprocessor

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IFAC Proceedings Volumes 2013年第28期46卷 221-226页

作者： Bernd Däne Alexander Pacholik Stephan Zschäck Wolfgang Fengler Christoph Ament Tobias Braune Computer Architecture and Embedded Systems Group Systems Analysis Group Ilmenau University of Technology 98684 Ilmenau Germany Tel: +49-3677-69-2825)

Computationally intensive algorithms for closed loop control and similar systems today can be implemented using reconfigurable FPGA devices. One approach is using soft microprocessor designs and implementing the algorithms as programs. This paper reports about a case study within an ongoing project that investigates a multi-core soft microprocessor solution for a closed-loop control application. Requirements within the project lead to a specialized processor design. Some results from experimental work are presented, demonstrating feasibility and efficiency of the approach.

关键词： embedded systems soft microprocessor signal processing floating-point real-time

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WLAN Location Sharing through a Privacy Observant architecture

WLAN Location Sharing through a Privacy Observant Architectu...

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International Conference on Communication systems Software and Middleware (COMSWARE)

作者： K. Muthukrishnan N. Meratnia M. Lijding G. Koprinkov P. Havinga Faculty of Computer Science Computer Architecture Design and Test for Embedded Systems group University of Twente Enschede Netherlands

In the last few years, WLAN has seen immense growth and it will continue this trend due to the fact that it provides convenient connectivity as well as high speed links. Furthermore, the infrastructure already exists in most public places and is cheap to extend. These advantages, together with the fact that WLAN covers a large area and is not restricted to line of sight, have led to developing many WLAN localization techniques and applications based on them. In this paper we present a novel calibration-free localization technique using the existing WLAN infrastructure that enables conference participants to determine their location without the need of a centralized system. The evaluation results illustrate the superiority of our technique compared to existing methods. In addition, we present a privacy observant architecture to share location information. We handle both the location of people and the resources in the infrastructure as services, which can be easily discovered and used. An important design issue for us was to avoid tracking people and giving the users control over who they share their location information with and under which conditions

关键词： Wireless LAN Privacy computer architecture Printers computer science System testing embedded system Wireless networks Portable computers IP networks

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Multi-domain transformational design flow for embedded systems

Multi-domain transformational design flow for embedded syste...

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International Conference on embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Kenneth C. Rovers Marcel D. van de Burgwal Jan Kuper André B. J. Kokkeler Gerard J. M. Smit Computer Architecture for Embedded Systems group CTIT Department of EEMCS University of Twente Enschede Netherlands

Current tools for embedded system design have limited support for modelling the interaction of the system with its physical environment. Furthermore, the natural representation of (streaming, real-time) applications with dataflow models is not supported by most tools. However, integrating multiple domains supports the design of complex interdisciplinary systems and enables model transformations. In this paper we discuss a unified approach, called UniTi, to handle continuous and discrete time models in a single framework, which includes the dataflow model as well. Our approach consists of a transformational design flow, expressed mathematically in a functional language. We formally distinguish the various domains and explain their interaction. In addition, we give guidelines for specifying algorithms such that these transformations can be applied. Our approach is illustrated with a non-trivial case study: beamforming in a phased array system.

关键词： Mathematical model Hardware Parallel processing computer architecture embedded systems Delay

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Deep Convolutional Autoencoder Applied for Noise Reduction in Range-Doppler Maps of FMCW Radars

Deep Convolutional Autoencoder Applied for Noise Reduction i...

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IEEE International Conference on Radar

作者： Marcio L. Lima de Oliveira Marco J. G. Bekooij Computer Architecture for Embedded Systems University of Twente Enschede The Netherlands NXP Semiconductors Eindhoven The Netherlands

ISBN: (数字)9781728168135

ISBN: (纸本)9781728168142

In this paper, we discuss the usage of deep Convolutional Autoencoders (CAE) for denoising Range-Doppler (RD) maps of an FMCW radar in a near-field situation with pedestrians and cyclists as moving objects. Traditional methods for noise reduction such as CFAR with Peak Detection (PD) have poor performance under highly noisy environments, especially when objects have low reflectivity, like pedestrians. We propose the use of Convolutional Autoencoders, in various configurations, to overcome those limitations. Due to its Artificial Neural Network nature, CAE can extract features, learn to identify patterns and recognize moving objects - such as humans and bicycles - while the traditional method acts passively. The results indicate that the usage of CAE overcame CFAR with PD by 76.8%, on average, for reconstructing objects in their correct positions. The results of this work may have many applications, for instance, detecting distant moving objects that are too faint for regular detection.

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