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IEEE International Conference on Radar

作者： Marcio L. Lima de Oliveira Marco J. G. Bekooij Computer Architecture for Embedded Systems University of Twente Enschede The Netherlands NXP Semiconductors Eindhoven The Netherlands

ISBN: (数字)9781728168135

ISBN: (纸本)9781728168142

In this paper, we discuss the usage of deep Convolutional Autoencoders (CAE) for denoising Range-Doppler (RD) maps of an FMCW radar in a near-field situation with pedestrians and cyclists as moving objects. Traditional methods for noise reduction such as CFAR with Peak Detection (PD) have poor performance under highly noisy environments, especially when objects have low reflectivity, like pedestrians. We propose the use of Convolutional Autoencoders, in various configurations, to overcome those limitations. Due to its Artificial Neural Network nature, CAE can extract features, learn to identify patterns and recognize moving objects - such as humans and bicycles - while the traditional method acts passively. The results indicate that the usage of CAE overcame CFAR with PD by 76.8%, on average, for reconstructing objects in their correct positions. The results of this work may have many applications, for instance, detecting distant moving objects that are too faint for regular detection.

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MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing

MEPNTC: A Standard-Cell Library Design Scheme Extending the ...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Anuradha C. Ranasinghe Sabih H. Gerez Chair of Computer Architecture for Embedded Systems Faculty of Electrical Engineering University of Twente Enschede Netherlands

ISBN: (数字)9781728197104

ISBN: (纸本)9781728197111

This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- V th operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- V th level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

关键词： Transform coding CMOS technology Libraries Hardware Energy efficiency Standards Resilience

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Transparent structural online test for reconfigurable systems

Transparent structural online test for reconfigurable system...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Mohamed S. Abdelfattah Lars Bauer Claus Braun Michael E. Imhof Michael A. Kochte Hongyan Zhang Jörg Henkel Hans-Joachim Wunderlich Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany Chair for Embedded Systems Karlsruhe Institute of Technology Germany

FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

关键词： Containers Field programmable gate arrays Testing Table lookup Runtime Random access memory Fabrics

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Adaptive resource allocation for streaming applications

Adaptive resource allocation for streaming applications

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International Conference on embedded computer systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Timon D. ter Braak Hermen A. Toersche André B. J. Kokkeler Gerard J. M. Smit Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente Enschede Netherlands

Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core architecture is commonly done at design-time to be able to analyze the complex design-space. However, such design-flows cannot deal with a dynamic platform or a dynamic set of applications. Hardware faults and resources claimed by other applications may render the assumed available resources inaccessible. To avoid the assumptions posed on the state of the platform by a fixed resource allocation, applications should be designed with location transparency in mind. Applications must be analyzed at design-time to determine the required resource budget, independent of which specific resources will be allocated. Sufficient performance can be guaranteed when such applications are mapped onto an architecture in which each resource is arbitrated using a budget scheduler. Within the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project, a many-core platform is developed that adheres to these requirements. Using the configuration features of the platform, the system is able to control at run-time what resources are being used by the applications. This paper shows that run-time resource allocation can effectively adapt to the available set of resources, providing partial distribution transparency to the user. As an example, a GNSS receiver is mapped to the platform containing faulty hardware components. A few resources remain critical, but in most cases the faulty components can be circumvented, such that adequate resources can be allocated to the application at run-time.

关键词： Hardware Routing Resource management Global Navigation Satellite systems Receivers Tiles Radio frequency

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Throughput optimizations for FPGA-based deep neural network inference

arXiv

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arXiv 2018年

作者： Posewsky, Thorbjörn Ziener, Daniel Hamburg21073 Germany Computer Architecture for Embedded Systems University of Twente Enschede7500 AE Netherlands

Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these computationally intensive networks are difficult to implement in embedded systems. Yet, the number of applications that can benefit from the mentioned possibilities is rapidly rising. In this paper, we propose novel architectures for the inference of previously learned and arbitrary deep neural networks on FPGAbased SoCs that are able to overcome these limitations. Our key contributions include the reuse of previously transferred weight matrices across multiple input samples, which we refer to as batch processing, and the usage of compressed weight matrices, also known as pruning. An extensive evaluation of these optimizations is presented. Both techniques allow a significant mitigation of data transfers and speed-up the network inference by one order of magnitude. At the same time, we surpass the data throughput of fully-featured x86-based systems while only using a fraction of their energy consumption. Copyright © 2018, The Authors. All rights reserved.

关键词： Deep neural networks

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Is the powersave governor really saving power?

Is the powersave governor really saving power?

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IEEE/ACM International Symposium on Cluster Computing and the Grid (CCGRID)

作者： Darong Huang Luis Costero David Atienza Embedded Systems Laboratory (ESL) EPFL Switzerland Dpto. of Computer Architecture and Automatics UCM Spain

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

A frequency scaling governor is critical for the performance management of cloud servers, as it enhances energy efficiency and helps to control operational temperatures, thereby ensuring system reliability. However, our in-depth analysis of the application’s performance and Dynamic Voltage and Frequency Scaling (DVFS) actions, alongside assessments of server power consumption and operating temperature, indicates that existing Linux scaling governors often fall into non-optimal DVFS strategies, especially for cloud applications with varying workloads and requests. This shortfall comes from the misleading CPU load metrics, which fail to accurately capture the applications’ true performance requirements and demands. In this context, we introduce a novel scaling governor named GreenDVFS. First, it identifies the optimal frequencies for the application in a range of workload scenarios. Optimal frequencies are used to maintain application performance, reduce server power consumption, and maintain a balanced operating temperature in different workload scenarios. Furthermore, we design a long short-term memory (LSTM)-based time series methodology to detect the real-time workloads of cloud applications accurately and timely. Building on these foundations, the proposed method takes optimal DVFS actions, tailored for cloud applications under different workload conditions, to optimize performance, energy efficiency, and temperature. The experimental results highlight the effectiveness of the proposed GreenDVFS, with up to 18% savings in energy consumption and a 30% decrease in operational temperature by comparing against the default Linux governor, all while not compromising the application’s performance. Such improvements help to optimize cloud computing operations for enhanced efficiency and sustainability.

关键词： Cloud computing Runtime Power demand Temperature Linux Time series analysis Energy efficiency Real-time systems Temperature control Servers

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Functional framework and hardware platform for dependability study in short range wireless embedded systems

Functional framework and hardware platform for dependability...

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2011 IEEE 17th International Mixed-Signals, Sensors and systems Test Workshop, IMS3TW 2011

作者： Senouci, B. Annema, A.J. Bentum, M.J. Kerkhoff, H.G. Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

ISBN: (纸本)9780769544793

A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software architecture is built. Dependability is one of the major challenges in these systems. Obviously in such systems, the attribute reliability has to be investigated for various components and at different abstractions levels. This paper presents a hardware platform for wireless system dependability analysis as an alternative for the time consuming global system simulation technique. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed methodology are two fold: first it takes care of the whole system (HW/SW part, mixed RF and wireless part) and second, the hardware platform enables to explore the application's reliability under real environmental conditions in order to study the effect of the environment threats on the system. © 2011 IEEE.

关键词： Abstracting

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Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

Module diversification: Fault tolerance and aging mitigation...

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IEEE International Test Conference

作者： Hongyan Zhang Lars Bauer Michael A. Kochte Eric Schneider Claus Braun Michael E. Imhof Hans-Joachim Wunderlich Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9781479908608

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.

关键词： Stress Circuit faults Aging Runtime Field programmable gate arrays Containers Reliability

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STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures 15

STRAP: Stress-aware placement for aging mitigation in runtim...

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IEEE International Conference on computer-Aided Design

作者： Hongyan Zhang Michael A. Kochte Eric Schneider Lars Bauer Hans-Joachim Wunderlich Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9781467383899

Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is amajor concern. We introduce the first cross-layer aging-aware placement method for accelerators in FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator placement at runtime, i.e. to which reconfigurable region an accelerator shall be reconfigured. Additionally, it optimizes logic placement at synthesis time to diversify the resource usage of individual accelerators, i.e. which CLBs of a reconfigurable region shall be used by an accelerator. Both layers together balance the intra- and inter-region stress induced by the application workload at negligible performance cost. Experimental results show significant reduction of maximum stress of up to 64% and 35%, which leads to up to 177% and 14% MTTF improvement relative to state-of-the-art methods w.r.t. HCI and BTI aging, respectively.

关键词： Stress Runtime Aging Transistors Table lookup Fabrics Field programmable gate arrays

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Investigating dependability of short-range wireless embedded systems through hardware platform based design

Investigating dependability of short-range wireless embedded...

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15th Euromicro Conference on Digital System Design, DSD 2012

作者： Senouci, B. Annema, A.J. Bentum, M.J. Kerkhoff, H.G. Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Computer Architecture for Embedded Systems /TDT Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

ISBN: (纸本)9780769547985

Most of the links in future wireless communication networks will be established over relatively short distances. This new direction in wireless communication is adopted and being developed by embedded multimedia applications leaders. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around reliability evaluation becomes an essential question to answer, and poses several challenges. Obviously, it's particularly difficult to investigate the reliability of such mixed HW/SW IPs based systems. Therefore, dependability has to be investigated at different abstractions levels, and for all components integrated into the system being designed. In this paper, we discuss the investigation of dependability in wireless short range systems. Firstly we show how a HW platform based dependability investigation can be a very interactive approach;secondly, we describe a real experience in building a wireless hardware platform for short range systems dependability analysis, and finally, based on this wireless network platform, we propose a dependability flow that takes care of the heterogeneous parts of the wireless embedded systems. © 2012 IEEE.

关键词： Reliability

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