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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Pepijn de Vos Michael Kirchhoff Daniel Ziener Symbiotic EDA University of Twente Enschede Netherlands Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany

ISBN: (纸本)9781665423021;9781665446228

In this paper, we propose an open source design flow for the low cost FPGAs from the company Gowin. Open source design tools are opening the door for custom extensions and modification in the design flow. The proposed design flow which supports almost all Gowin FPGA resources, is based on well-known open source tools, like Yosys and nextpnr, as well as on our proposed open source bitstream generator. The necessary architectural details of the FPGA family are gathered by input fuzzing and comparisons with the vendor tool flow. Experimental results show an almost similar performance as the vendor tools.

关键词： Companies Tools Logic gates Fuzzing Software Generators Design tools

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A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

TechRxiv

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TechRxiv 2023年

作者： Menbari, Ahmad Rahimi, Hemin Jahanirad, Hadi Ziener, Daniel The Department of Electrical Engineering University of Kurdistan Sanandaj Iran The Department of Computer Architecture and Embedded Systems Ilmenau University of Technology Ilmenau Germany

In the realm of 3D monolithic integrated circuits, inter-layer vias are prone to defects during fabrication, assembly, and operation that necessitates robust Built-In Self-Test solutions. This paper introduces an innovative BIST design aimed at the detection and localization of different types of faults in irregularly placed ILVs using a walking pattern methodology. In the proposed BIST methodology, the ILVs are clustered based on the fault occurrence probability distribution. Then, an effective detection approach is developed for all stuck-at faults, bridging faults, and almost all multiple faults in a single cluster. This approach allows designers to adjust different parameters such as fault coverage percentage, fault localization, and test time in alignment with specific requisites. The proposed BIST method reduces test configurations to two and test time to just 20 cycles by dividing ILVs into more clusters, overcoming a key limitation of recent approach. This methodology also demonstrates improved efficiency in terms of power consumption, area, and hardware utilization, particularly for large-scale benchmarks. For instance, when considering LU32PEENG and the scenario where ILVs are divided into 64 clusters, the power, area, and hardware overhead are 0.82% and 1.03%, and 1.14%, respectively. © 2023, CC BY.

关键词： Built-in self test

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EVOAL: A Domain-Specific Language-Based Approach to Optimisation

EVOAL: A Domain-Specific Language-Based Approach to Optimisa...

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Congress on Evolutionary Computation

作者： Bernhard J. Berger Christina Plump Rolf Drechlser Institute of Embedded Systems Hamburg University of Technology Hamburg Germany DFKI GmbH-Cyber-Physical Systems Bremen Germany University Bremen - Computer Architecture Bremen Germany

Adapting optimisation algorithms, such as evolutionary algorithms, to a problem is a necessity. The required collection and exchange of domain information is an important but tedious task in real-world projects involving several experts from different areas of expertise (e.g. the domain and the optimisation area). This paper presents a structured approach that allows the experts to systematically provide their knowledge using domain-specific languages. The presented approach defines a different language for the involved experts that enables them to add their knowledge and use the information provided by other experts. The languages are extensible, allowing the addition of new optimisation aspects without changing the actual language. These languages are the front-end to a versatile open-source optimisation tool, that we built, enabling the actual execution of the optimisation. It additionally provides features for surrogate models as well as data generation and different benchmarks for evaluation. Conducting a user study, we show that the language is suitable to express the domain knowledge and domain experts can use the language to describe their domain knowledge after a short introduction. This way, the approach reduces the effort for domain experts in providing their information. As a side effect, the complete configuration of the optimisation execution through these languages allows an easy and reliable reproduction.

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Introduction of local memory elements in instruction set extensions

Introduction of local memory elements in instruction set ext...

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Design Automation Conference

作者： P. Biswas V. Choudhary K. Atasu L. Pozzi P. Ienne Nikil Dutt Center for Embedded Computer Systems University of California Irvine CA USA Processor Architecture Laboratory Swiss Federal Institute of Technology Lausanne Switzerland

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Unraveling the Mystery of NVIDIA's Unified Memory for Safety-Critical GPU systems

Unraveling the Mystery of NVIDIA's Unified Memory for Safety...

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Euromicro Symposium on Digital System Design

作者： Xabier Arauzo Irune Yarza Leonidas Kosmidis Alejandro J. Calderón Marcos Rodriguez Reliable Embedded Systems Ikerlan Technology Research Centre Computer Architecture Universitat Politècnica de Catalunya Mondragón Spain Reliable Embedded Systems Ikerlan Technology Research Centre Mondragón Spain Computer Architecture Universitat Politècnica de Catalunya Barcelona Super Computing Centre (BSC) Barcelona Spain

In the domain of safety-critical systems there is an increasing need for more compute-capable and higher performance devices. This comes from the dramatic increase on the software complexity caused by the newest intelligent and autonomous systems. Graphics Processing Units (GPUs), as multi-processing accelerators, are an ideal choice in this aspect due to their ability to handle big amount of data and computations. In order to ease the challenging task of programming such devices, vendors are continuously adding features, such as Unified Memory (UM), which allow the programmers to reduce their developing time on GPU applications. However, the use of GPU poses several challenges on safety-critical systems due to its close source nature and proprietary implementation. Therefore, this paper shows a deeper insight on how this feature works and present a way of exploiting this knowledge to reduce the execution time of applications using NVIDIA's UM feature. We demonstrate that these optimizations can make the data migrations predictable and reduce the required time.

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Case Study on Design and Evaluation of a Multi-Soft-Core Processor

Case Study on Design and Evaluation of a Multi-Soft-Core Pro...

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International Conference and Workshop on Computing and Communication (IEMCON)

作者： Michael Kirchhoff Lothar Wagner Bernd Däne Detlef Streitferdt Wolfgang Fengler Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany Group for Software Systems and Process Informatics Technische Universität Ilmenau Ilmenau Germany

ISBN: (纸本)9781728125312

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. The trend for soft-core processors, as well as mainstream CPUs (central processing units), leads to multi-core architectures. Both the necessary memory architectures and the compilers play an important role in this process. In this paper, a novel method that aims at minimizing the necessary memory resources on the FPGA while maximizing the processing speed of any given algorithm is described. In the first step, an application-specializable multi-soft-core processor architecture is presented that is capable of solving problems while adhering to hard real-time deadlines. Its special architecture and other necessary features are discussed. Furthermore, a method for the generation of optimized machine code for each processor core as well as hard real-time compatible deadlock handling mechanisms are presented. Selected algorithms are implemented to demonstrate the functionality and efficiency of the realized approach for different configurations of the multi-soft-core processor architecture.

关键词： Microprocessors Multicore processing Memory architecture Multiprocessor interconnection Field programmable gate arrays Field programmable gate arrays Memory architecture macroprocessor Parallel processor interconnection PROCESSOR soft-core Processor Core embedded system development Processor architectures Mechanical Code central processing units hard real-time

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Towards safe data flow processing by integration of design by contract in deterministic UML activities

Towards safe data flow processing by integration of design b...

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XXII International Symposium on Information, Communication and Automation Technologies, ICAT

作者： Zamira Daw Marcus Vetter Josef Boercsoek Institute of Embedded Systems Hochschule Mannheim-University of Applied Sciences Mannheim Germany Department of Computer Architecture and System Programming University of Kassel Kassel Germany

Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For safety related applications, this pipeline has to be able to identify and react to failures. The DMOSES model-driven development method uses deterministic UML activities to describe and implement data flow processing. This method ensures deterministic behavior of concurrent processing. Design by Contract defines formal, precise and verifiable interfaces for software components. We propose a development method for safe data flow processing based on the integration of this concept in deterministic UML activities. This integration allows the identification of errors by detection of contracts violation. This paper presents an extension of the DMOSES tool for contracts verification at the model level and their monitoring at runtime.

关键词： Unified modeling language Contracts Monitoring embedded systems Object oriented modeling Safety Pins

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Certifiable Development Process for Information Processing in the Measurement Domain on the Base of 3W-Models

Certifiable Development Process for Information Processing i...

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IEEE Annual computer Software and Applications Conference Workshops (COMPSACW)

作者： Irina Gushchina Wolfgang Fengler Jirka Ciemala Detlef Streitferdt Computer Architecture and Embedded Systems Group Ilmenau University of Technology Ilmenau Germany Software Architectures and Product Lines Group Ilmenau University of Technology Ilmenau Germany

The paper presents a certifiable development process applicable to hardware and software development for information processing in the measurement domain, especially the dynamic weighing technology. Thereby it is based on the developments of prototypes for new and predecessor systems and product stages. Particular attention is paid to the possibility of calibration.

关键词： Prototypes Mathematical model embedded systems Hardware Safety Measurement uncertainty Field programmable gate arrays

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A multi-lead ECG classification based on random projection features

A multi-lead ECG classification based on random projection f...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Iva Bogdanova Francisco Rincón David Atienza Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne Switzerland Department of Computer Architecture and Automation Complutense University of Madrid Spain

This paper presents a novel method for classification of multi-lead electrocardiogram (ECG) signals. The feature extraction is based on the random projection (RP) concept for dimensionality reduction. Furthermore, the classification is performed by a neuro-fuzzy classifier. Such a model can be easily implemented on portable systems for practical applications in both health monitoring and diagnostic purposes. Moreover, the RP implementation on portable systems is very challenging featuring both energy efficiency and feasibility. The proposed method is tested on a 12-lead ECG database consisting of 20 beats during normal sinus rhythm, 20 beats with myocardial infarction and 20 beats showing cardiomyopathy for 60 different subjects. The experiments give a recognition rate of 100% for a small number of RP coefficients (only 25), i.e. after a considerable dimensionality reduction of the input ECG signal. The results are very promising, not only from the classification performance point of view, but also while targeting a low-complexity feature extraction in terms of computation requirements and memory usage for real-time operation on a wireless wearable sensor platform.

关键词： Electrocardiography Feature extraction Databases Pragmatics Wireless sensor networks Wireless communication computer architecture

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Functional Framework and Hardware Platform for Dependability Study in Short Range Wireless embedded systems

Functional Framework and Hardware Platform for Dependability...

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IEEE International Mixed-Signals, Sensors, and systems Test Workshop, IMS3TW

作者： Benaouneur Senouci Anne-Johan Annema Mark Bentum Hans G. Kerkhoff Telecommunication Engineering Group Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group University of Twente Enschede Netherlands Computer Architecture for Embedded Systems Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software architecture is built. Dependability is one of the major challenges in these systems. Obviously in such systems, the attribute reliability has to be investigated for various components and at different abstractions levels. This paper presents a hardware platform for wireless system dependability analysis as an alternative for the time consuming global system simulation technique. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed methodology are two fold: first it takes care of the whole system (HW/SW part, mixed RF and wireless part) and second, the hardware platform enables to explore the application's reliability under real environmental conditions in order to study the effect of the environment threats on the system.

关键词： Wireless communication Hardware Reliability System-on-a-chip computer architecture Libraries embedded systems

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