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13th IEEE Annual Information Technology, Electronics and Mobile Communication Conference, IEMCON 2022

作者： Kirchhoff, Michael Debo, Saad Nau, Johannes Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany

ISBN: (数字)9781665463164

ISBN: (纸本)9781665463164

Accurate indoor position tracking and analysis of the movement dynamics of autonomous driving systems are important challenges when it comes to automatize industrial processing, supply chains or warehouses. In this paper, the authors present an indoor position tracking architecture with a novel sensor fusion approach for autonomous robots in three-dimensional space. For robots to be able to drive autonomous, they need information of their position, speed and orientation in 3D-space. With the presented architecture, position information is provided by the Indoor Positioning System (IPS) and orientation information as well as velocity are determined by the Inertial Navigation System (INS). The proposed tracking architecture combines those informations with a sensor fusion approach, thus enabling the autonomous driving system. © 2022 IEEE.

关键词： Real time systems

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A Petri net table model applied to classic and agile project management

A Petri net table model applied to classic and agile project...

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2019 International Workshop on Petri Nets and Software Engineering, PNSE 2019

作者： Weichenhain, Maxi Fengler, Wolfgang Computer Architecture and Embedded Systems Group Technische Universität Ilmenau Germany

The world of project management (PM) is diverse and extensive, as is the resulting tool selection on the market. Despite the wide variety of tools available, many PM activities are carried out using self-developed spreadsheets that have been tailored to meet the needs of the project. The authors have evaluated experiences from several completed projects and recognizes the need for a systematic model based on a formalised and tool-independent table structure. The goal of this work is to use a powerful Petri net (PN) model for mapping and simulation, taking advantage of the model's benefits. Thus, an effective and flexible methodology for PM can be realised. In order to use the concept of PN for this purpose, appropriated extensions and necessary interpretations from the area of high-level timed Petri nets must be used. Moreover, PM has to be brought to the same description level as PN. The concept of this proposed method is to enter all data, initial plan inputs and intermediate status updates into a defined table structure. A PN is then automatically generated in the background or updated to reflect the current status of the project. Simulations should be performed on the PN models, and their results should be put back into the table. The advantages of the PN concept can thus be fully exploited and become useful for a project manager, even if he or she does not have any PN knowledge. This article presents an overview of the proposed formalised methodology, its suitability to PM, and its benefits. The method itself can be applied to a wide range of projects. Focus is placed on how to transfer certain areas of PM into the introduced PN constructs and interfaces. Examples are used to illustrate how to transform PM activities and their related information into the selected PNs. © 2019 CEUR Workshop Proceedings. All rights reserved.

关键词： Petri nets

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A Complete Open Source Design Flow for Gowin FPGAs

A Complete Open Source Design Flow for Gowin FPGAs

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Pepijn de Vos Michael Kirchhoff Daniel Ziener Symbiotic EDA University of Twente Enschede Netherlands Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany

ISBN: (纸本)9781665423021;9781665446228

In this paper, we propose an open source design flow for the low cost FPGAs from the company Gowin. Open source design tools are opening the door for custom extensions and modification in the design flow. The proposed design flow which supports almost all Gowin FPGA resources, is based on well-known open source tools, like Yosys and nextpnr, as well as on our proposed open source bitstream generator. The necessary architectural details of the FPGA family are gathered by input fuzzing and comparisons with the vendor tool flow. Experimental results show an almost similar performance as the vendor tools.

关键词： Companies Tools Logic gates Fuzzing Software Generators Design tools

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Case Study on Design and Evaluation of a Multi-Soft-Core Processor

Case Study on Design and Evaluation of a Multi-Soft-Core Pro...

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International Conference and Workshop on Computing and Communication (IEMCON)

作者： Michael Kirchhoff Lothar Wagner Bernd Däne Detlef Streitferdt Wolfgang Fengler Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany Group for Software Systems and Process Informatics Technische Universität Ilmenau Ilmenau Germany

ISBN: (纸本)9781728125312

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. The trend for soft-core processors, as well as mainstream CPUs (central processing units), leads to multi-core architectures. Both the necessary memory architectures and the compilers play an important role in this process. In this paper, a novel method that aims at minimizing the necessary memory resources on the FPGA while maximizing the processing speed of any given algorithm is described. In the first step, an application-specializable multi-soft-core processor architecture is presented that is capable of solving problems while adhering to hard real-time deadlines. Its special architecture and other necessary features are discussed. Furthermore, a method for the generation of optimized machine code for each processor core as well as hard real-time compatible deadlock handling mechanisms are presented. Selected algorithms are implemented to demonstrate the functionality and efficiency of the realized approach for different configurations of the multi-soft-core processor architecture.

关键词： Microprocessors Multicore processing Memory architecture Multiprocessor interconnection Field programmable gate arrays Field programmable gate arrays Memory architecture macroprocessor Parallel processor interconnection PROCESSOR soft-core Processor Core embedded system development Processor architectures Mechanical Code central processing units hard real-time

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Self-Awareness for Autonomous systems

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PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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Accurate dead code detection in embedded C code by arithmetic constraint solving 1

Accurate dead code detection in embedded C code by arithmeti...

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1st Workshop on Satisfiability Checking and Symbolic Computation, SC-Square 2016

作者： Neubauer, Felix Scheibler, Karsten Becker, Bernd Mahdi, Ahmed Fränzle, Martin Teige, Tino Bienmüller, Tom Fehrer, Detlef Department of Computer Architecture University of Freiburg Germany Research Group Hybrid Systems Carl von Ossietzky University of Oldenburg Germany BTC Embedded Systems AG Oldenburg Germany Sick AG Waldkirch Germany

Unreachable code fragments in software, despite not having a negative impact on the functional behavior, can have a bad effect in other areas, such as code optimization or coverage-based code validation and certification. Especially the latter is important in industrial, safety critical environments, where detecting such dead code is a major goal to adjust the coverage of software tests. In the context of embedded systems we focus on C programs which are reactive, control-oriented, and floating-point dominated. Such programs are either automatically generated from Simulink-plus-Stateflow models or hand-written according to coding guidelines. While there are various techniques - e. g. abstract interpretation or Counterexample guided abstraction refinement (CEGAR) - to deal with individual issues of this domain, there is none which can cover all of them. The AVACS transfer project T1 aims at the combination of these techniques in order to provide an accurate and efficient dead code detection. In this paper we present the ideas and goals of the project as well as the current status (including very promising experimental results) and future challenges. Copyright © by the paper's authors.

关键词： Formal verification

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Accurate ICP-based floating-point reasoning 16

Accurate ICP-based floating-point reasoning

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Formal Methods in computer Aided Design (FMCAD)

作者： Karsten Scheibler Felix Neubauer Ahmed Mahdi Martin Fränzle Tino Teige Tom Bienmüller Detlef Fehrer Bernd Becker Chair of Computer Architecture University of Freiburg Germany Research Group Hybrid Systems Carl von Ossietzky University of Oldenburg Germany BTC Embedded Systems AG Oldenburg Germany Sick AG Waldkirch Germany

ISBN: (纸本)9780983567868

In scientific and technical software, floating-point arithmetic is often used to approximate arithmetic on physical quantities natively modeled as reals. Checking properties for such programs (e.g. proving unreachability of code fragments) requires accurate reasoning over floating-point arithmetic. Currently, most of the SMT-solvers addressing this problem class rely on bit-blasting. Recently, methods based on reasoning in interval lattices have been lifted from the reals (where they traditionally have been successful) to the floating-point numbers. The approach presented in this paper follows the latter line of interval-based reasoning, but extends it by including bitwise integer operations and cast operations between integer and floating-point arithmetic. Such operations have hitherto been omitted, as they tend to define sets not concisely representable in interval lattices, and were consequently considered the domain of bit-blasting approaches. By adding them to interval-based reasoning, the full range of basic data types and operations of C programs is supported. Furthermore, we propose techniques in order to mitigate the problem of aliasing during interval reasoning. The experimental results confirm the efficacy of the proposed techniques. Our approach outperforms solvers relying on bit-blasting as well as the existing interval-based SMT-solver.

关键词： Cognition Lattices Iterative closest point algorithm Open area test sites Context Computational modeling Encoding

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A dataflow inspired programming paradigm for coarse-grained reconfigurable arrays

A dataflow inspired programming paradigm for coarse-grained ...

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10th International Symposium on Reconfigurable Computing: architectures, Tools, and Applications, ARC 2014

作者： Niedermeier, A. Kuper, Jan Smit, Gerard J. M. Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente Netherlands

ISBN: (纸本)9783319059594

In this paper, we present a new approach towards programming coarse-grained reconfigurable arrays (CGRAs) in an intuitive, dataflow inspired way. Based on the observation that available CGRAs are usually programmed using C, which lacks proper support for instruction-level parallelism, we instead started from a dataflow perspective combined with a language that inherently supports parallel structures. Our programming paradigm decouples the local functionality of a core from the global flow of data, i.e. the kernels from the routing. We will describe the ideas of our programming paradigm and also the language and compiler itself. Our complete system, including the CGRA, the programming language and the compiler, was developed using Haskell, which leads to a complete, sound system. We finish the paper with the implementation of a number of algorithms using our system. © 2014 Springer International Publishing Switzerland.

关键词： Program compilers

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Designing a control application by using a specialized multi-core soft microprocessor

Designing a control application by using a specialized multi...

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12th IFAC Conference on Programmable Devices and embedded systems, PDeS 2013

作者： Däne, Bernd Pacholik, Alexander Zschäck, Stephan Fengler, Wolfgang Ament, Christoph Braune, Tobias Computer Architecture and Embedded Systems Group Ilmenau University of Technology 98684 Ilmenau Germany Systems Analysis Group Ilmenau University of Technology 98684 Ilmenau Germany

ISBN: (纸本)9783902823533

Computationally intensive algorithms for closed loop control and similar systems today can be implemented using reconfigurable FPGA devices. One approach is using soft microprocessor designs and implementing the algorithms as programs. This paper reports about a case study within an ongoing project that investigates a multi-core soft microprocessor solution for a closed-loop control application. Requirements within the project lead to a specialized processor design. Some results from experimental work are presented, demonstrating feasibility and efficiency of the approach. © IFAC.

关键词： Signal processing

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Designing a Control Application by Using a Specialized Multi-Core Soft Microprocessor

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IFAC Proceedings Volumes 2013年第28期46卷 221-226页

作者： Bernd Däne Alexander Pacholik Stephan Zschäck Wolfgang Fengler Christoph Ament Tobias Braune Computer Architecture and Embedded Systems Group Systems Analysis Group Ilmenau University of Technology 98684 Ilmenau Germany Tel: +49-3677-69-2825)

关键词： embedded systems soft microprocessor signal processing floating-point real-time

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