Current tools for embedded system design have limited support for modelling the interaction of the system with its physical environment. Furthermore, the natural representation of (streaming, real-time) applications w...
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Current tools for embedded system design have limited support for modelling the interaction of the system with its physical environment. Furthermore, the natural representation of (streaming, real-time) applications with dataflow models is not supported by most tools. However, integrating multiple domains supports the design of complex interdisciplinary systems and enables model transformations. In this paper we discuss a unified approach, called UniTi, to handle continuous and discrete time models in a single framework, which includes the dataflow model as well. Our approach consists of a transformational design flow, expressed mathematically in a functional language. We formally distinguish the various domains and explain their interaction. In addition, we give guidelines for specifying algorithms such that these transformations can be applied. Our approach is illustrated with a non-trivial case study: beamforming in a phased array system.
Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core archit...
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Streaming applications often have latency and throughput requirements due to timing critical signal processing, or the time critical interaction with their environment. Mapping such applications to a multi-core architecture is commonly done at design-time to be able to analyze the complex design-space. However, such design-flows cannot deal with a dynamic platform or a dynamic set of applications. Hardware faults and resources claimed by other applications may render the assumed available resources inaccessible. To avoid the assumptions posed on the state of the platform by a fixed resource allocation, applications should be designed with location transparency in mind. Applications must be analyzed at design-time to determine the required resource budget, independent of which specific resources will be allocated. Sufficient performance can be guaranteed when such applications are mapped onto an architecture in which each resource is arbitrated using a budget scheduler. Within the Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project, a many-core platform is developed that adheres to these requirements. Using the configuration features of the platform, the system is able to control at run-time what resources are being used by the applications. This paper shows that run-time resource allocation can effectively adapt to the available set of resources, providing partial distribution transparency to the user. As an example, a GNSS receiver is mapped to the platform containing faulty hardware components. A few resources remain critical, but in most cases the faulty components can be circumvented, such that adequate resources can be allocated to the application at run-time.
High performance image processing applications area challenging field when targeting embedded processing. Field programmable gate arrays (FPGA) receive a growing interest as implementation platforms, but these solutio...
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High performance image processing applications area challenging field when targeting embedded processing. Field programmable gate arrays (FPGA) receive a growing interest as implementation platforms, but these solutions have to compete with the state of the art in image processing, which is codefined by graphics processing units (GPU). This paper provides a case study which analyzes the potential of embedded or hybrid implementation on FPGA and GPU for image stack processing in a white light interferometry (WLI) application.
A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software arc...
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A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of a few meters. Behind these embedded applications, a complex Hardware/Software architecture is built. Dependability is one of the major challenges in these systems. Obviously in such systems, the attribute reliability has to be investigated for various components and at different abstractions levels. This paper presents a hardware platform for wireless system dependability analysis as an alternative for the time consuming global system simulation technique. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed methodology are two fold: first it takes care of the whole system (HW/SW part, mixed RF and wireless part) and second, the hardware platform enables to explore the application's reliability under real environmental conditions in order to study the effect of the environment threats on the system.
Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embeddedsystems. Reliability problems arise from permanent erro...
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Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embeddedsystems. Reliability problems arise from permanent erro...
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Due to the continuous shrinking of the transistor sizes which is strongly driven by Moore's law, reliability becomes a dominant design challenge for embeddedsystems. Reliability problems arise from permanent errors due to manufacturing, process variations, aging as well as soft errors. As a result, the hardware will consist of unreliable components and hence, the development of embeddedsystems has to change fundamentally. Therefore, we propose a dependability-aware design approach for hardware systems through integrating dependability into a state-of-the-art system-level design language. Our approach is based on SystemC and extends the Program State Machine model to explicitly observe, diagnose, and compensate faulty behavior. Different compensation mechanisms like run-time reconfiguration or mechanisms for error propagation can be used by the designer during refinement. They are controlled by a new exception-like mechanism. Furthermore, our approach aims to integrate functional verification as well as dependability verification with respect to given fault models.
In the last few years, WLAN has seen immense growth and it will continue this trend due to the fact that it provides convenient connectivity as well as high speed links. Furthermore, the infrastructure already exists ...
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In the last few years, WLAN has seen immense growth and it will continue this trend due to the fact that it provides convenient connectivity as well as high speed links. Furthermore, the infrastructure already exists in most public places and is cheap to extend. These advantages, together with the fact that WLAN covers a large area and is not restricted to line of sight, have led to developing many WLAN localization techniques and applications based on them. In this paper we present a novel calibration-free localization technique using the existing WLAN infrastructure that enables conference participants to determine their location without the need of a centralized system. The evaluation results illustrate the superiority of our technique compared to existing methods. In addition, we present a privacy observant architecture to share location information. We handle both the location of people and the resources in the infrastructure as services, which can be easily discovered and used. An important design issue for us was to avoid tracking people and giving the users control over who they share their location information with and under which conditions
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