咨询与建议

限定检索结果

文献类型

  • 10 篇 会议
  • 1 篇 期刊文献

馆藏范围

  • 11 篇 电子文献
  • 0 种 纸本馆藏

日期分布

学科分类号

  • 5 篇 工学
    • 4 篇 电子科学与技术(可...
    • 4 篇 计算机科学与技术...
    • 3 篇 仪器科学与技术
    • 3 篇 软件工程
    • 2 篇 电气工程
    • 2 篇 控制科学与工程
    • 1 篇 机械工程
    • 1 篇 动力工程及工程热...
    • 1 篇 信息与通信工程
  • 2 篇 管理学
    • 2 篇 管理科学与工程(可...
    • 2 篇 工商管理
  • 1 篇 经济学
    • 1 篇 应用经济学
  • 1 篇 法学
    • 1 篇 社会学
  • 1 篇 理学
    • 1 篇 数学

主题

  • 3 篇 logic gates
  • 2 篇 observability
  • 2 篇 costs
  • 2 篇 hardware
  • 1 篇 registers
  • 1 篇 telecommunicatio...
  • 1 篇 circuit partitio...
  • 1 篇 logic testing
  • 1 篇 application soft...
  • 1 篇 error correction
  • 1 篇 electronic mail
  • 1 篇 circuit synthesi...
  • 1 篇 vectors
  • 1 篇 authentication
  • 1 篇 monitoring
  • 1 篇 divide-and-conqu...
  • 1 篇 wireless sensor ...
  • 1 篇 system-on-chip
  • 1 篇 silicon
  • 1 篇 circuit testing

机构

  • 4 篇 computer design ...
  • 2 篇 malaviya nationa...
  • 2 篇 computer design ...
  • 1 篇 computer archite...
  • 1 篇 indian institute...
  • 1 篇 ic design - digi...
  • 1 篇 computer enginee...
  • 1 篇 computer archite...
  • 1 篇 engineering lab ...
  • 1 篇 state key labora...
  • 1 篇 cisco systems ba...
  • 1 篇 electrical enggi...
  • 1 篇 computer design ...
  • 1 篇 dept. of compute...
  • 1 篇 tomsk state univ...
  • 1 篇 texas instrument...
  • 1 篇 philips research...
  • 1 篇 center for advan...
  • 1 篇 pvt. ltd. bangal...
  • 1 篇 mobile embedded ...

作者

  • 3 篇 singh virendra
  • 3 篇 virendra singh
  • 2 篇 g. kiefer
  • 2 篇 h. vranken
  • 2 篇 a. irion
  • 1 篇 larssonz erik
  • 1 篇 k. r. vinutha
  • 1 篇 zhao danella
  • 1 篇 anzhela matrosov...
  • 1 篇 prasanth v.
  • 1 篇 vinay n.s.
  • 1 篇 gaurx m.s.
  • 1 篇 yuan peiyan
  • 1 篇 mohammed abdul r...
  • 1 篇 s. mukhopadhyay
  • 1 篇 fujiwara hideo
  • 1 篇 zhao mengdi
  • 1 篇 matrosova anzhel...
  • 1 篇 v prasanth
  • 1 篇 s. dey

语言

  • 11 篇 英文
检索条件"机构=Computer Design and Test Lab"
11 条 记 录,以下是1-10 订阅
排序:
Robust detection of soft errors using delayed capture methodology
Robust detection of soft errors using delayed capture method...
收藏 引用
16th IEEE International On-Line testing Symposium, IOLTS 2010
作者: Prasanth, V. Singh, Virendra Parekhji, Rubin Computer Design and Test Lab. Indian Institute of Science Bangalore India Pvt. Ltd. Bangalore India
With the scaling of technology node and voltage levels, the susceptibility of logic to soft errors is increasing. Hence it is very important to take care of soft errors in the combinational logic along with those in t... 详细信息
来源: 评论
Effective domain partitioning for multi-clock domain IP core wrapper design under power constraints
Effective domain partitioning for multi-clock domain IP core...
收藏 引用
作者: Yu, Thomas Edison Yoneda, Tomokazu Zhao, Danella Fujiwara, Hideo Computer Design and Test Lab Nara Institute of Science and Technology Ikoma-shi 630-0101 Japan Center For Advanced Computer Studies University of Louisiana at Lafayette United States
The rapid advancement of VLSI technology has made it possible for chip designers and manufacturers to embed the components of a whole system onto a single chip, called System-on-Chip or SoC. SoCs make use of pre-desig... 详细信息
来源: 评论
Fault grading using Instruction-Execution graph
Fault grading using Instruction-Execution graph
收藏 引用
East-West design and test Symposium
作者: Vinutha, K.R. Singh, Virendra Matrosova, Anzhela Gaur, M.S. Computer Design and Test Lab. Indian Institute of Science Bangalore India Tomsk State University Russia Malaviya National Institute of Technology Jaipur India
Functional test sequences are used in testing to target faults that are not detected by structural test. However, evaluating the stuck-at fault coverage of the functional test sequence by the gate-level fault simulati... 详细信息
来源: 评论
Thermal aware test scheduling for stacked multi-chip-modules
Thermal aware test scheduling for stacked multi-chip-modules
收藏 引用
East-West design and test Symposium
作者: Vinay, N.S. Rawaty, Indira Larssonz, Erik Gaurx, M.S. Singh, Virendra Cisco Systems Bangalore India Electrical Enggineering Dept. Engineering College Ajmer India Dept. of Computer Science Linkoping University Linkoping Sweden Computer Engineering Dept. Malaviya National Institute of Technology Jaipur India Computer Design and Test Lab. Indian Institute of Science Bangalore India
In an attempt to increase the area utilization of multi-chip packages, manufacturers have started looking at 3D packaging. The 3D structures have either dies or chips stacked one above the other. These 3D structures h... 详细信息
来源: 评论
Circuit partitioning for efficient logic BIST synthesis
Circuit partitioning for efficient logic BIST synthesis
收藏 引用
design, Automation and test in Europe Conference and Exhibition
作者: A. Irion G. Kiefer H. Vranken H.-J. Wunderlich Computer Architecture Lab University of Stuttgart Stuttgart Germany IC Design - Digital Design & Test Philips Research Laboratories Eindhoven AA The Netherlands
A divide-and-conquer approach using circuit partitioning is presented, which can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis algorithms contain steps with a time complexity which increas... 详细信息
来源: 评论
Data aware, low cost error correction for wireless sensor networks
Data aware, low cost error correction for wireless sensor ne...
收藏 引用
IEEE Conference on Wireless Communications and Networking
作者: S. Mukhopadhyay D. Panigrahi S. Dey Mobile Embedded Systems Design and Test Lab Department of Electrical and Computer Engineering University of California San Diego USA
One or the main challenges in adoption and deployment of wireless networked sensing applications is ensuring reliable sensor data collection and aggregation, while satisfying the low-cost, low-energy operating constra... 详细信息
来源: 评论
SSTKR: Secure and testable Scan design through test Key Randomization
SSTKR: Secure and Testable Scan Design through Test Key Rand...
收藏 引用
Asian test Symposium (ATS)
作者: Mohammed Abdul Razzaq Virendra Singh Adit Singh Computer Design and Test Lab Indian Institute of Science Bangalore India Department of Electrical Engineering Aubum University Auburn USA
Scan test is the standard method, practiced by industry, that has consistently provided high fault coverage due to high controllability and high observability. The scan chain allows to control and observe the internal... 详细信息
来源: 评论
Fault grading using Instruction-Execution graph
Fault grading using Instruction-Execution graph
收藏 引用
East-West design & test Symposium (EWDTS)
作者: K. R. Vinutha Virendra Singh Anzhela Matrosova M. S. Gaur Computer Design and Test Lab. Indian Institute of Science Bangalore India Tomsk State University Russian Federation Malaviya National Institute of Technology Jaipur India
Functional test sequences are used in testing to target faults that are not detected by structural test. However, evaluating the stuck-at fault coverage of the functional test sequence by the gate-level fault simulati... 详细信息
来源: 评论
Circuit partitioning for efficient logic BIST synthesis  01
Circuit partitioning for efficient logic BIST synthesis
收藏 引用
Proceedings of the conference on design, automation and test in Europe
作者: A. Irion G. Kiefer H. Vranken H. Wunderlich Computer Architecture Lab University of Stuttgart Breitwiesenstr. 20/22 70565 Stuttgart Germany Philips Research Laboratories IC Design - Digital Design & Test Prof. Holstlaan 4 5656 AA Eindhoven The Netherlands
来源: 评论
Derating based hardware optimizations in soft error tolerant designs
Derating based hardware optimizations in soft error tolerant...
收藏 引用
VLSI test Symposium
作者: V Prasanth Virendra Singh Rubin Parekhji Indian Institute of Science Bangalore Karnataka IN Computer Design and Test Lab Indian institute of Science Bangalore India Texas Instruments (India) Pvt. Ltd. Bangalore India
Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a... 详细信息
来源: 评论