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IEEE Transactions on Intelligent Vehicles 2024年第9期9卷 1-12页

作者： Liu, Chunhong Zhao, Mengdi Wang, Huaichen Cheng, Bo Liu, Jialei Yuan, Peiyan Engineering Lab of Intelligence Business & Internet of Things and School of Computer and Information Engineering Henan Normal University Xinxiang China State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China Hubei Key Laboratory of Power System Design and Test for Electrical Vehicle and School of Computer Engineering Hubei University of Arts and Science Xiangyang China

Vehicle edge computing (VEC) offers users low-latency and high-reliability services by using computational resources at the network's edge. Nevertheless, because of inadequate infrastructure and limited resources, computation-intensive and delay-sensitive vehicle applications cannot be performed efficiently at the edge. Therefore, several studies have used the idle resources of parked vehicles to assist in computation offloading. In this paper, we propose a parked vehicle-assisted vehicle edge computing architecture considering multi-agent collaboration, including intelligent vehicles and edge servers. Additionally, we propose a framework for a parallel Internet of Vehicles (IoV) utilizing computational experiment. The service provider is assigned the role of owning VEC resources and recruiting parking vehicle resources. The model was constructed by using the resource consumption-service relationship of both offloading parties to ensure service quality. First, a Stackelberg game model was constructed based on the interaction between requesting vehicles and a service provider. The latter was the leader, and the requesting vehicles were the followers. The Nash equilibrium for optimal pricing and offloading allocations was attained and verified, and a distributed gradient-based equilibrium algorithm was designed to solve the Stackelberg game model and obtain the final decision through mutual communication. The method also protects the privacy of participants and respects the willingness of requesting vehicles to offload. Finally, the simulation experiments confirmed that the proposed algorithm can achieve game equilibrium. Furthermore, it outperformed state-of-the-art algorithms in improving the service provider's utility. IEEE

关键词： Vehicles

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Derating based hardware optimizations in soft error tolerant designs

Derating based hardware optimizations in soft error tolerant...

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VLSI test Symposium

作者： V Prasanth Virendra Singh Rubin Parekhji Indian Institute of Science Bangalore Karnataka IN Computer Design and Test Lab Indian institute of Science Bangalore India Texas Instruments (India) Pvt. Ltd. Bangalore India

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e.g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show up to 23% reduction in the hardware overhead when considering individual and combined derating factors.

关键词： Abstracts Microprogramming Hardware Clocks Logic gates

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SSTKR: Secure and testable Scan design through test Key Randomization

SSTKR: Secure and Testable Scan Design through Test Key Rand...

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Asian test Symposium (ATS)

作者： Mohammed Abdul Razzaq Virendra Singh Adit Singh Computer Design and Test Lab Indian Institute of Science Bangalore India Department of Electrical Engineering Aubum University Auburn USA

Scan test is the standard method, practiced by industry, that has consistently provided high fault coverage due to high controllability and high observability. The scan chain allows to control and observe the internal signals of a chip. However, this property also facilitates hackers to use scan architecture as a means to breach chip security. This paper addresses this issue by proposing a new method called Secure and testable Scan design through test Key Randomization(SSTKR). SSTKR is a key based method to prevent hackers from stealing secret information. Linear Feedback Shift Register (LFSR) is used to generate authentication keys to be embedded in test vectors. Unique key is used for every test vector which prevents scan based side channel attacks effectively. Any attempt to steal secret information will lead to a randomized response. SSTKR has very low area and test time overhead without performance penalty. Our approach also facilitates in-field test of the chip.

关键词： Vectors Authentication computer hacking testing Logic gates Observability

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Robust detection of soft errors using delayed capture methodology

Robust detection of soft errors using delayed capture method...

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16th IEEE International On-Line testing Symposium, IOLTS 2010

作者： Prasanth, V. Singh, Virendra Parekhji, Rubin Computer Design and Test Lab. Indian Institute of Science Bangalore India Pvt. Ltd. Bangalore India

ISBN: (纸本)9781424477227

With the scaling of technology node and voltage levels, the susceptibility of logic to soft errors is increasing. Hence it is very important to take care of soft errors in the combinational logic along with those in the sequential elements. In this paper, a novel method is proposed to detect the presence of soft errors in both combinational and sequential logic. In this method, flipflops are grouped and parity is computed for each group twice - once at the input of the flip-flops and next at the output. Later, the parity at the inputs and outputs is compared to detect the presence of soft errors. The effectiveness of the technique is shown through experimental results. © 2010 IEEE.

关键词： Flip flop circuits

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Fault grading using Instruction-Execution graph

Fault grading using Instruction-Execution graph

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East-West design and test Symposium

作者： Vinutha, K.R. Singh, Virendra Matrosova, Anzhela Gaur, M.S. Computer Design and Test Lab. Indian Institute of Science Bangalore India Tomsk State University Russia Malaviya National Institute of Technology Jaipur India

ISBN: (纸本)9781424495566

Functional test sequences are used in testing to target faults that are not detected by structural test. However, evaluating the stuck-at fault coverage of the functional test sequence by the gate-level fault simulation can be very time consuming. To obtain a fast estimation of the fault coverage, we describe a metric to grade the test sequence using Instruction-Execution graph. The metric is based on the set of registers the circuit traverses under the test sequence. Using this information in combination with the observability and controllability of the register, the test sequence is graded. Experimental results on Parwan processor show the effectiveness of the metric in ranking the test sequence based on their fault coverage. © 2010 IEEE.

关键词： Grading

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Thermal aware test scheduling for stacked multi-chip-modules

Thermal aware test scheduling for stacked multi-chip-modules

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East-West design and test Symposium

作者： Vinay, N.S. Rawaty, Indira Larssonz, Erik Gaurx, M.S. Singh, Virendra Cisco Systems Bangalore India Electrical Enggineering Dept. Engineering College Ajmer India Dept. of Computer Science Linkoping University Linkoping Sweden Computer Engineering Dept. Malaviya National Institute of Technology Jaipur India Computer Design and Test Lab. Indian Institute of Science Bangalore India

ISBN: (纸本)9781424495566

In an attempt to increase the area utilization of multi-chip packages, manufacturers have started looking at 3D packaging. The 3D structures have either dies or chips stacked one above the other. These 3D structures have low thermal capabilities, and hence the thermal issues get aggravated during testing. In this paper, thermal aware test scheduling techniques for stacked structures is proposed. Care is taken to schedule the stacked partitions appropriately to prevent local heating and achieve uniform vertical temperature spread. Concurrent testing of dies is considered for reduced test time and existing test architecture is employed. The widely used global peak power model gives a pessimistic estimate of the power profile. A new partition scheme is proposed for the power profile based on power variations and true power. This scheme of power profile partitioning which is a trade-off between a cycle accurate model and global peak model offers both flexibility during scheduling and also reduces total false power. The power profile partitions are scheduled through algorithms based on heuristics. System model of the 3D stack is obtained from the linear RC-models after considering the various factors that affect the heat flow and die temperatures. Simulation results show that the proposed technique achieves uniform temperature spread across the 3D structure. © 2010 IEEE.

关键词： Economic and social effects

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Fault grading using Instruction-Execution graph

Fault grading using Instruction-Execution graph

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East-West design & test Symposium (EWDTS)

作者： K. R. Vinutha Virendra Singh Anzhela Matrosova M. S. Gaur Computer Design and Test Lab. Indian Institute of Science Bangalore India Tomsk State University Russian Federation Malaviya National Institute of Technology Jaipur India

关键词： Registers Circuit faults Observability Measurement Logic gates Integrated circuit modeling Electronic mail

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Effective domain partitioning for multi-clock domain IP core wrapper design under power constraints

Effective domain partitioning for multi-clock domain IP core...

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作者： Yu, Thomas Edison Yoneda, Tomokazu Zhao, Danella Fujiwara, Hideo Computer Design and Test Lab Nara Institute of Science and Technology Ikoma-shi 630-0101 Japan Center For Advanced Computer Studies University of Louisiana at Lafayette United States

The rapid advancement of VLSI technology has made it possible for chip designers and manufacturers to embed the components of a whole system onto a single chip, called System-on-Chip or SoC. SoCs make use of pre-designed modules, called IP-cores, which provide faster design time and quicker time-to-market. Furthermore, SoCs that operate at multiple clock domains and very low power requirements are being utilized in the latest communications, networking and signal processing devices. As a result, the testing of SoCs and multi-clock domain embedded cores under power constraints has been rapidly gaining importance. In this research, a novel method for designing power-aware test wrappers for embedded cores with multiple clock domains is presented. By effectively partitioning the various clock domains, we are able to increase the solution space of possible test schedules for the core. Since previous methods were limited to concurrently testing all the clock domains, we effectively remove this limitation by making use of bandwidth conversion, multiple shift frequencies and properly gating the clock signals to control the shift activity of various core logic elements. The combination of the above techniques gains us greater flexibility when determining an optimal test schedule under very tight power constraints. Furthermore, since it is computationally intensive to search the entire expanded solution space for the possible test schedules, we propose a heuristic 3-D bin packing algorithm to determine the optimal wrapper architecture and test schedule while minimizing the test time under power and bandwidth constraints. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.

关键词： System-on-chip

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Data aware, low cost error correction for wireless sensor networks

Data aware, low cost error correction for wireless sensor ne...

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IEEE Conference on Wireless Communications and Networking

作者： S. Mukhopadhyay D. Panigrahi S. Dey Mobile Embedded Systems Design and Test Lab Department of Electrical and Computer Engineering University of California San Diego USA

One or the main challenges in adoption and deployment of wireless networked sensing applications is ensuring reliable sensor data collection and aggregation, while satisfying the low-cost, low-energy operating constraints of such applications. A wireless sensor network is inherently vulnerable to different sources of unreliability resulting in transient failures. Existing reliability techniques that address transient failures in circuits and communication channels incur prohibitively high energy, bandwidth and cost overheads in the sensor nodes. In this paper we investigate application-level error correction techniques for sensor networks that exploit the properties of sensor data to eliminate any overhead on the sensor nodes, at the expense of nominal buffer requirements at the data aggregator nodes, which are much less cost/energy constrained. Our approach involves use of spatio-temporal correlations in sensor data, the goals of the application, and its vulnerability to various errors. We present our error-correction algorithm and evaluate it through simulations using real and synthetic sensor data. Experimental results validate the feasibility of our approach to provide high degree of reliability in sensor data aggregation, without imposing overheads on sensor nodes.

关键词： Costs Error correction Wireless sensor networks Telecommunication network reliability Power system transients Crosstalk Circuits Application software Communication channels Monitoring

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Circuit partitioning for efficient logic BIST synthesis

Circuit partitioning for efficient logic BIST synthesis

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design, Automation and test in Europe Conference and Exhibition

作者： A. Irion G. Kiefer H. Vranken H.-J. Wunderlich Computer Architecture Lab University of Stuttgart Stuttgart Germany IC Design - Digital Design & Test Philips Research Laboratories Eindhoven AA The Netherlands

ISBN: (纸本)0769509932

A divide-and-conquer approach using circuit partitioning is presented, which can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis algorithms contain steps with a time complexity which increases more than linearly with the circuit size. By extracting sub-circuits which are almost constant in size, BIST synthesis for very large designs may be possible within linear time. The partitioning approach does nor require any physical modifications of the circuit under test. Experiments show that significant performance improvements can be obtained at the cost of a longer test application time or a slight increase in silicon area for the BIST hardware.

关键词： Logic circuits Built-in self-test Circuit synthesis Circuit testing Logic testing Costs Integrated circuit testing Silicon Hardware Logic design

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