Software risk evaluation is a process for identifying, analysing, and developing mitigation strategies for risk in a software intensive system while it is in development. This paper presents a systematic approach for ...
Software risk evaluation is a process for identifying, analysing, and developing mitigation strategies for risk in a software intensive system while it is in development. This paper presents a systematic approach for the estimation of software risk and cost using esrcTool. This tool is based on software risk assessment and estimation model. In this model function point approach is employed as an input variable to estimate the source of uncertainty, i.e. measurement error, model error, and assumption error. To show the validity of our tool, we have considered the project developed by our students.
Construction firms look for opportunities to operate overseas to earn high returns. Firm's competitiveness is very important in determining the entry location to the host country. Thus, there is a need for the fir...
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Many practical routing problems such as BGA, PGA, pin redistribution and test fixture routing involve routing with interchangeable pins. These routing problems, especially package layout, are becoming more difficult t...
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ISBN:
(纸本)9780818675973
Many practical routing problems such as BGA, PGA, pin redistribution and test fixture routing involve routing with interchangeable pins. These routing problems, especially package layout, are becoming more difficult to do manually due to increasing speed and I/O. Currently, no commercial or university router is available for this task. In this paper, we unify these different problems as instances of the interchangeable pin routing (IPR) problem, which is NP-complete. By representing the solution space with flows in a triangulated routing network instead of grids, we developed a min-cost max-flow heuristic considering only the most important cuts in the design. The heuristic handles multiple layers, prerouted nets, and all-angle, octilinear or rectilinear wiring styles. Experiments show that the heuristic is very effective on most practical examples. It had been used to route industry designs with thousands of interchangeable pins.
This paper presents the New Systolic Language as a general solution to the problem of systolic programming. The language provides a simple programming interface for systolic algorithms suitable for different hardware ...
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This paper presents the New Systolic Language as a general solution to the problem of systolic programming. The language provides a simple programming interface for systolic algorithms suitable for different hardware platforms and software simulators. The New Systolic Language hides the details and potential hazards of inter-processor communication, allowing data flow only via abstract systolic data streams. Data flows and systolic cell programs for the co-processor are integrated with host functions, enabling a single file to specify a complete systolic program.< >
The multicore processors, which are widely available in recent times, have great potential to achieve significant performance improvement of the Digital Image Processing Algorithms. Due to the availability of inherent...
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After introducing the Primitive Bridge Function, a characteristic function describing the behavior of bridged components, we present a theorem for detecting feedback bridge faults. We discuss two different methods of ...
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After introducing the Primitive Bridge Function, a characteristic function describing the behavior of bridged components, we present a theorem for detecting feedback bridge faults. We discuss two different methods of bridge fault simulation, one of which is new, and present experimental results relating the relative efficiency of the two methods. We conclude that the new simulation method, Wire Memory bridge fault simulation, is more efficient--especially for larger circuits.
Fanout routing for Ball Grid Array(BGA) packages becomes non-trivial when the I/O pin count increases. When the number of I/Os gets larger and larger, the number of I/Os we can put on a package may not limited by the ...
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ISBN:
(纸本)9780818672132
Fanout routing for Ball Grid Array(BGA) packages becomes non-trivial when the I/O pin count increases. When the number of I/Os gets larger and larger, the number of I/Os we can put on a package may not limited by the available area but sometimes by the ability to fan them out on the next level of interconnect---the PCB or MCM substrate. This paper presents an efficient algorithm (EVENFANOUT) which generates the optimal uniform distribution of wires. We have found the three cuts that is decisive on the routability of the package using EVENFANOUT. These decisive cuts form the base for design optimization of the package.
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