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Developing a prototype concurrent design tool for composite topside structures

NAVAL ENGINEERS JOURNAL 1997年第3期109卷 279-290页

作者： Dirlik, S Hambric, S Azarm, S Marquardt, M Hellman, A Bartlett, S Castelli, V Steve Dirlik:began his career at the Naval Surface Warfare Center Carderock Division in 1981 as an aerospace engineer co-op student. He completed his bachelor of science degree in aeropace and ocean engineering from Virginia Polytechnic Institute and State University in 1985 and his master of science degree in aerospace engineering from the University of Maryland in 1990. Mr. Dirlik recently completed a master of science program in applied physics at The Johns Hopins University and currently works in the Radar Cross Section and Target Physics Branch of the Signatures Directorate at the Naval Surface Warfare Center Corderoke Division. He has worked on Navy low observable programs since 1990. Stephen Hambric:is a research associate at the Applied Research Laboratory at The Pennsylvania State University. He received his B. S. and M.S. degree in mechanical engineering from Virginia Polytechnic Institute and State University and his D. Sc. in mechnical engineering from the George Washington University. He has worked on several computer aided multidiscikplinary design and optimization projects over the years including an automated propeller design system and a structural acoustic optimization capability. Dr. Shpour Azarm:is currently working as an associate professor with the Design and Manufacturing Group of the Department of Mechanical Engineering at the University of maryland at College Park. Dr Azarm's expertise is in the areas of optimization-based designed and concurrent design and optimization of multidisciplinary systems. He was a consultant at Black & Decker Corporation (summer 1996) and worked as a Navy senior summer faculty fellow (summer 1995) and a NASA summer faculty fellow (summer 1994). He was a visiting scientist at NASA Langley Research Center for Multidisciplinary Analysis and Applied Structural Optimzatiom at the University of Siegen in Germany (spring 1992) and the Design Institute of the Technical University of Denmark (summer 1990). Dr Azarm was an associate technical editor of the ASME Jour

A prototype concurrent engineering tool has been developed for the preliminary design of composite topside structures for modern navy warships. This tool, named GELS for the Concurrent engineering of Layered Structures, provides designers with an immediate assessment of the impacts of their decisions on several disciplines which are important to the performance of a modern naval topside structure, including electromagnetic interference effects (EMI), radar cross section (RCS), structural integrity, cost, and weight. Preliminary analysis modules in each of these disciplines are integrated to operate from a common set of design variables and a common materials database. Performance in each discipline and an overall fitness function for the concept are then evaluated. A graphical user interface (GUI) is used to define requirements and to display the results from the technical analysis modules. Optimization techniques, including feasible sequential quadratic programming (FSQP) and exhaustive search are used to modify the design variables to satisfy all requirements simultaneously. The development of this tool, the technical modules, and their integration are discussed noting the decisions and compromises required to develop and integrate the modules into a prototype conceptual design tool.

关键词： Warships

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An ASIC for fast grey-scale dilation

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MICROPROCESSORS AND MICROSYSTEMS 1996年第2期20卷 89-95页

作者： Andreadis, I Gasteratos, A Tsalides, P Laboratory of Electronics Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi 67100 Greece

The design and VLSI implementation of a new ASIC which performs the operation of grey-scale dilation using both image and structuring element threshold decomposition is presented in this paper. The minimum rate of external operations of this ASIC is 30 MPix/sec and it can handle 3 x 3 pixel images and structuring elements of up to 4-bit resolution. The high speed of operation is achieved using the pipelining technique. The ASIC is implemented using a DLM, 1.0 mu m, N-well, CMOS process provided by the European Silicon Structures (ES2), and it occupies a silicon area of 5.48 x 5.77 mm = 31.61 mm(2). It is intended to be used in machine vision applications, where the need for short processing times is crucial (e.g. robotics and military systems).

关键词： mathematical morphology VLSI ASIC

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Improvement of the majority gate algorithm for grey scale dilation/erosion

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ELECTRONICS LETTERS 1996年第9期32卷 806-807页

作者： Gasteratos, A Andreadis, I Tsalides, P Department of Electrical and Computer Engineering Section of Electronics and Information Systems Technology Laboratory of Electronics Democritus University of Thrace Xanthi Greece

An improvement of the majority gale algorithm suitable for grey scale morphological operations is presented in the Letter. The redundancy of temporal signals led to a simplified hardware implementation. It is shown that maximin operators can be computed by the same circuit. A new pipelined systolic array architecture based oil this circuit is illustrated for dilation/erosion operations.

关键词： mathematical morphology computer vision

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A new hardware module for automated visual inspection based on a cellular automaton architecture

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JOURNAL OF INTELLIGENT & ROBOTIC SYSTEMS 1996年第1期16卷 89-102页

作者： Andreadis, I Karafyllidis, I Tzionas, P Thanailakis, A Tsalides, P Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering Democritus University of Thrace 67100 Xanthi Greece

This paper presents the design and VLSI implementation of a new automated visual inspection system based on a cellular automaton architecture, suitable for circular object inspection. Cellular Automata (CA) transform the area of the object of interest into a number of evolution steps in the CA space. The proposed technique does not require the extraction of image features, such as boundary length and total area, which are computationally expensive in other methods. The die size dimensions of the chip, for a 16 x 16 pixel image, are 3.73 mm x 3.09 mm = 11.52 mm(2) and its maximum frequency of operation is 25 MHz. Experimental results using computer-generated images, as well as real images obtained and processed through a commercial vision system, showing the suitability of the proposed hardware module for detecting circular objects, are also presented. Targeted applications include inspection tasks (accept/reject operations) of circular objects, such as tablets in the pharmaceutical industry, and detection of uncoated areas, foreign objects and level of bake in the confectionery and food industry.

关键词： visual inspection detection of uncoated areas cellular automata ASICs

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Controlled node splitting 6th

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Proceedings of the 6th International Conference on Compiler Construction, CC'96

作者： Janssen, Johan Corporaal, Henk Delft University of Technology Department of Electrical Engineering Section Computer Architecture and Digital Systems 2600 GA Delft 5031 Netherlands

ISBN: (纸本)9783540610533

To exploit instruction level parallelism in programs over multiple basic blocks, programs should have reducible control flow graphs. However not all programs satisfy this property. A new method, called Controlled Node Splitting (CNS), for transforming irreducible control flow graphs to reducible control flow graphs is presented. CNS duplicates nodes of the control flow graph to obtain reducible control flow graphs. CNS results in a minimum number of splits and a minimum number of duplicates. Since the computation time to find the optimal split sequence is large, a heuristic has been developed. The results of this heuristic are close to the optimum. Straightforward application of node splitting may result in an average code size increase of 235%. CNS with the heuristic limits the increase to only 3%. © Springer-Verlag Berlin Heidelberg 1996.

关键词： Compilation Control flow graphs Instruction level parallelism Irreducibility Node splitting Reducibility

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Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits

Pulse-driven dual-rail logic gate family based on rapid sing...

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International Symposium on Advanced Research in Asynchronous Circuits and Systems

作者： M. Maezawa I. Kurosawa Y. Kameda T. Nanya Electron Devices Division Superconductivity Electronics Section Electrotechnical Laboratory Tsukuba Ibaraki Japan Computer Science Tokyo Institute of Technology Tokyo Japan Department of Mathematical Engineering and Information Physics University of Tokyo Japan

We present a pulse-driven asynchronous logic gate family based on a high-speed, low-power Josephson-junction device of rapid single-flux-quantum (RSFQ) circuits. Dual-rail logic is used and clock-free operation is realized. The proper operation of the circuits is confirmed by the numerical simulation which shows logic delays are about 60 ps for an AND and about 80 ps for an XOR. Power consumption is estimated to be 10 /spl mu/W/gate.

关键词： Logic gates Logic devices Josephson junctions Clocks Timing Pulse circuits Logic circuits Delay estimation Superconductivity Numerical simulation

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DESIGN AND VLSI IMPLEMENTATION OF AN ASIC FOR REAL-TIME MANIPULATION OF DIGITAL COLOR IMAGES

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MICROPROCESSORS AND MICROSYSTEMS 1995年第5期19卷 247-253页

作者： ANDREADIS, I STAVROGLOU, K TSALIDES, P Laboratory of Electronics Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering 67100 Xanthi Greece

This paper presents the design and VLSI implementation, on a single chip, of a new real-time colour space converter, which performs the transformation of the RCB colour coordinates to the intensity, hue and saturation (IHS) colour space. This high speed VLSI chip is designed to work at 13.3 MHz and can process high resolution colour images of up to 697 pixels per horizontal line. Its minimum rate of operation is 133 MIPS. The high speed of operation was achieved by pipelining the data in a vector fashion. The chip was implemented using a DLM, 1.0 mu m, N-well, CMOS process provided by European Silicon Structures and the die size dimensions for the chip are 5.669 mm x 6.144 mm = 34.830 mm(2). The chip is intended to be used as the front end of colour machine vision systems in inspection tasks and in autonomous applications, where the need for short processing times is crucial. Finally, simulation results exhibiting the usefulness of the IHS colour space transform using the proposed ASIC and real colour image data are also presented.

关键词： COLOR REAL-TIME IMAGE PROCESSING

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IMAGE-ENHANCEMENT USING COLOR INFORMATION

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INTERNATIONAL JOURNAL OF REMOTE SENSING 1995年第12期16卷 2285-2289页

作者： ANDREADIS, I GLAVAS, E TSALIDES, P [a] Laboratory of Electronics Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece

A new image enhancement technique using the Intensity, Hue and Saturation (IHS) colour space is presented in this letter Experimental results illustrating the enhancement capabilities of the proposed technique are given. Comparative examples of the proposed technique to the grey level histogram equalisation technique are also included.

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Cellular automata-based collision-free robot path planning

Cellular automata-based collision-free robot path planning

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Asia and South Pacific Design Automation Conference

作者： P. Tzionas P. Tsalides A. Thanailakis Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering School of Engineering Democritus University of Thrace Xanthi Greece

This paper presents a new parallel algorithm for collision-free path planning of a diamond-shaped robot among arbitrarily-shaped obstacles and its implementation in VLSI. The proposed algorithm is based on the computational geometry concept known as the "Voronoi diagram", which is constructed through the time evolution of Cellular Automata, after an initial phase during which the boundaries of obstacles are identified and coded with respect to their orientation.

关键词： Robotics and automation Path planning Information systems Computational geometry Motion planning Very large scale integration Shape Parallel algorithms Parallel robots Land vehicles

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Development and application of MCAL tools for marine radar instruction

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computer Applications in engineering Education 1995年第4期3卷 259-259页

作者： Guirguis, S. Korany, E. Abdel-Bary, A. Institute of Graduate Studies and Research Alexandria University Alexandria Egypt Shawkat K. Guirguis:obtained the BSc and M.Sc. degrees in Computer Science and Automatic Control Faculty of Engineering Alexandria University in 1981 and 1984 respectively. In 1988 he obtained a PhD degree in Electronics and Communications Faculty of Engineering Cairo University co-supervised by the Imperial College of Science and Technology University of London where he spent two years as an academic visitor. His current research interests include software quality management multimedia automatic programming and decision support systems. He is currently a lecturer of Computer Science at the Institute of Graduate Studies & Research Alexandria University. Ezzat A. Korany:received the BS degree in Electrical Engineering (Electronics Section) from the University of Alexandria Egypt in 1971 the MS degree in Electrical Engineering (Computer Section) from Ain Shams University Cairo Egypt in 1977 and the PhD degree in Electrical Engineering (Digital Systems) from Florida Institute of Technology U.S.A. in 1982. He is currently an associate professor of Computer Science at the Institute of Graduate Studies & Research University of Alexandria. His research interests are in data communications and multimedia applications computer networks image processing and pattern recognition. Abdel-Latif A. Abdel-Bary:obtained the BEng degree in Electronics Technology from Arab Maritime Transport Academy in 1986. In 1995 he obtained the MSc degree in Information Technology from the Institute of Graduate Studies & Research Alexandria University. His current research interests include ICAL hypermedia and automatic programming.

In this article a multimedia computer-assisted learning (MCAL) system is presented. The major objective of this work was to investigate the potential of using such systems as tools for transferring instructional course information through various types of computer media as opposed to the classic CAL systems. The philosophy and techniques employed to design the system are investigated. Usage of the implemented system and its merits have been illustrated through its application to teach engineering students and technicians the theory and concepts of marine radar. System design, implementation, test, and revision phases are presented and discussed.

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