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International Joint Conference on Neural Networks (IJCNN)

作者： W.-C. Fang B.J. Sheu O.T.-C. Chen Jet Propulsion Laboratory Advanced Computer Systems and Technology Section California Institute of Technology Pasadena CA USA Department of Electrical Engineering Signal and Image Processing Institute University of Southern California Los Angeles CA USA

The frequency-sensitive competitive learning (FSCL) algorithm and its associated VLSI neuroprocessor have been developed for adaptive vector quantisation (AVQ). Simulation results show that the FSCL algorithm is capable of producing a good-quality codebook for AVQ at high compression ratios of more than 20 in real time. This VLSI neural-network-based vector quantization design includes a fully parallel vector quantizer and a pipelined codebook generator to provide an effective data compression scheme. It provides a computing capability as high as 3.33 billion connections per second. Its performance can achieve a speedup of 750 compared with SUN-3/60 and a compression ratio of 33 at a signal-to-noise ratio of 23.81 dB.< >

关键词： Very large scale integration Image coding Frequency Neural networks Power capacitors Vector quantization CMOS technology Image reconstruction Speech coding Data compression

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Real-time high-ratio image compression using adaptive VLSI neuroprocessors

Real-time high-ratio image compression using adaptive VLSI n...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： B.J. Sheu W.-C. Fang Department of Electrical Engineering Signal and Image Processing Institute University of Southern California Los Angeles CA USA Jet Propulsion Laboratory Advanced Computer Systems and Technology Section California Institute of Technology Pasadena CA USA

An adaptive VLSI neuroprocessor based on vector quantization algorithm has been developed for real-time high-ratio image compression applications. This VLSI neural-network-based vector quantization (NNVQ) module combines a fully parallel vector quantizer with a pipelined codebook generator for a broad area of data compression applications. The NNVQ module is capable of producing good-quality reconstructed data at high compression ratios more than 20. The vector quantizer chip has been designed, fabricated, and tested. It contains 64 inner-product neural units and a high-speed extendable winner-take-all block. This mixed-signal chip occupies a compact silicon area of 4.6*6.8 mm/sup 2/ in a 2.0- mu m scalable CMOS technology. The throughput rate of the 2- mu m NNVQ module is 2 million vectors per second and its equivalent computation power is 3.33 billion connections per second.< >

关键词： Image coding Very large scale integration Vector quantization Neural networks Data compression High performance computing Clustering algorithms Application software Image reconstruction CMOS technology

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computer-SYSTEM ARCHITECTURE CONCEPTS FOR FUTURE COMBAT SYSTEMS

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NAVAL ENGINEERS JOURNAL 1990年第3期102卷 43-62页

作者： ZITZMAN, LH FALATKO, SM PAPACH, JL Dr. Lewis H. Zitzman:is the group supervisor of the Advanced Systems Design Group Fleet Systems Department The Johns Hopkins University Applied Physics Laboratory (JHU/APL). He has been employed at JHU/APL since 1972 performing applied research in computer science and in investigating and applying advanced computer technologies to Navy shipboard systems. He is currently chairman of Aegis Computer Architecture Data Bus and Fiber Optics Working Group from which many concepts for this paper were generated. Dr. Zitzman received his B.S. degree in physics from Brigham Young University in 1963 and his M.S. and Ph.D. degrees in physics from the University of Illinois in 1967 and 1972 respectively. Stephen M. Falatko:was a senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated for the majority of this effort. He is currently employed at ManTech Services Corporation. During his eight-year career first at The Johns Hopkins University Applied Physics Laboratory and currently with ManTech Mr. Falatko's work has centered around the development of requirements and specifications for future Navy systems and the application of advanced technology to Navy command and control systems. He is a member of both the Computer Architecture Fiber Optics and Data Bus Working Group and the Aegis Fiber Optics Working Group. Mr. Falatko received his B.S. degree in aerospace engineering with high distinction from the University of Virginia in 1982 and his M.S. degree in applied physics from The Johns Hopkins University in 1985. Mr. Falatko is a member of Tau Beta Pi Sigma Gamma Tau the American Society of Naval Engineers and the U.S. Naval Institute. Janet L. Papach:is a section leader and senior engineering analyst in the Combat Systems Engineering Department Comptek Research Incorporated. She has ten years' experience as an analyst supporting NavSea Spa War and the U.S. Department of State. She currently participates in working group efforts under Aegis Combat System Doctrin

This paper sets forth computer systems architecture concepts for the combat system of the 2010–2030 timeframe that satisfy the needs of the next generation of surface combatants. It builds upon the current Aegis computer systems architecture, expanding that architecture while preserving, and adhering to, the Aegis fundamental principle of thorough systems engineering, dedicated to maintaining a well integrated, highly reliable, and easily operable combat system. The implementation of these proposed computer systems concepts in a coherent architecture would support the future battle force capable combat system and allow the expansion necessary to accommodate evolutionary changes in both the threat environment and the technology then available to effectively counter that threat. Changes to the current Aegis computer architecture must be carefully and effectively managed such that the fleet will retain its combat readiness capability at all times. This paper describes a possible transition approach for evolving the current Aegis computer architecture to a general architecture for the future. The proposed computer systems architecture concepts encompass the use of combinations of physically distributed, microprocessor-based computers, collocated with the equipment they support or embedded within the equipment itself. They draw heavily on widely used and available industry standards, including instruction set architectures (ISAs), backplane busses, microprocessors, computer programming languages and development environments, and local area networks (LANs). In this proposal, LANs, based on fiber optics, will provide the interconnection to support system expandability, redundancy, and higher data throughput rates. A system of cross connected LANs will support a high level of combat system integration, spanning the major warfare areas, and will facilitate the coordination and development of a coherent multi-warfare tactical picture supporting the future combatant command st

关键词： computer Architecture

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SYNCHRONIZATION OF ASYNCHRONOUS CONCURRENT PROCESSES USING CELLULAR AUTOMATA

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PARALLEL COMPUTING 1989年第2期11卷 163-169页

作者： ADAMIDES, E TSALIDES, P THANAILAKIS, A Laboratory of Electrotechnical and Electronic Materials Technology Electronics and Computer Engineering Section Department of Electrical Engineering School of Engineering Democritus University of Thrace 67100 Xanthi Greece

The use of a cellular processors network to synchronize a system of asynchronous concurrent processes in a trully parallel manner is demonstrated. The associated problems of deadlock and indefinite postponement are considered with particular reference to the classical synchronization problem known as the Dining Philosophers problem. A hardware model for the solution of the problem is presented. A more practical example such as the use of cellular processors for the synchronization of a multiprocessor system is also considered.

关键词： asynchronous concurrent process synchronization Cellular automata cellular processor networks resource sharing

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Data buffering: run-time versus compile-time support

Data buffering: run-time versus compile-time support

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Third International Conference on Architectural Support for Programming Languages and Operating Systems Architectural Support for Programming Languages and Operating Systems

作者： Mulder, Hans Section Computer Architecture and Digital Systems Department of Electrical Engineering Delft University of Technology PO Box 5031 2600 AG Delft The Netherlands

ISBN: (纸本)0897913000

Data-dependency, branch, and memory-access penalties are main constraints on the performance of high-speed microprocessors. The memory-access penalties concern both penalties imposed by external memory (e.g. cache) or by under utilization of the local processor memory (e.g. registers). This paper focuses solely on methods of increasing the utilization of data memory, local to the processor (registers or register-oriented buffers).A utilization increase of local processor memory is possible by means of compile-time software, run-time hardware, or a combination of both. This paper looks at data buffers which perform solely because of the compile-time software (single register sets); those which operate mainly through hardware but with possible software assistance (multiple register sets); and those intended to operate transparently with main memory implying no software assistance whatsoever (stack buffers). This paper shows that hardware buffering schemes cannot replace compile-time effort, but at most can reduce the complexity of this effort. It shows the utility increase of applying register allocation for multiple register sets. The paper also shows a potential utility decrease inherent to stack buffers. The observation that a single register set, allocated by means of interprocedural allocation, performs competitively with both multiple register set and stack buffer emphasizes the significance of the conclusion

关键词： computer operating systems

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A flexible VLSI core for an adaptable architecture 22

A flexible VLSI core for an adaptable architecture

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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Stravers, Paul Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture. The SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures;tools for synthesizing architectures from application or application-area;VLSI cell libraries and tools for quick generation of application-specific processors;a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates on the micro-architecture framework of SCARCE and outlines the process of generating VLSI processors. © 1990 ACM.

关键词： Cost effectiveness

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Cost-effective design of application specific VLIW processors using the SCARCE framework 22

Cost-effective design of application specific VLIW processor...

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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Mulder, Hans Portier, Robert J. Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology P.O. Box 5031 Delft2600 GA Netherlands

ISBN: (纸本)0897913248

Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs;especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these costs to be reduced, but the flexibility often reduces efficiency. VLIW is a new and promising concept for the design of low-cost, high-performance parallel computer systems. We suggest that the VLIW concept can also be used as a basis for cost-effective design of application-specific processors which must exploit application-resident parallelism. The SCARCE (SCalable ARChitecture Experiment) framework, an approach for cost-effective design of application-specific processors, provides features which allow the design of retargetable VLIW architectures. However, a retargetable VLIW architecture is only effective if there is a retargetable VLIW compiler. Since a VLIW compiler is an essential part of the VLIW architecture, tradeoffs must be made between the variety of VLIW architectures and the compiler complexity. We suggest that limiting the flexibility of the retargetable VLIW architecture does not necessary reduce the application space. This paper discusses the issues related to the design of a retargetable VLIW processor architecture and compiler within the SCARCE framework. © 1990 ACM.

关键词： Very long instruction word architecture

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DOAS: An object oriented architecture supporting secure languages 22

DOAS: An object oriented architecture supporting secure lang...

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22nd Annual Workshop on Microprogramming and Microarchitecture, MICRO 1989

作者： Van De Goor, A.J. Corporaal, H. Section Digital Systems and Computer Architecture Faculty of Electrical Engineering Delft University of Technology Mekelweg 4 P.O. Box 5031 Delft2600 AG Netherlands

ISBN: (纸本)0897913248

Current software engineering practice heavily relies on the reliability of software implementation languages and underlying architectures. However, both the currently used languages, as well as the traditional architectures suffer from a shortage of built-in security. In this paper, an architecture is presented, which is heavily influenced by two properties of secure languages: coercion and exception handling. It is shown that proper design decisions lead to an architecture having a compact data representation, allowing both generic and nongeneric instructions. The architecture is object oriented, and object addressing is under control of the operand stream, with optimalisation possibilities to bypass descriptor inspection. © 1990 ACM.

关键词： Object oriented programming

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An architecture framework for application-specific and scalable architectures 89

An architecture framework for application-specific and scala...

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Proceedings of the 16th annual international symposium on computer architecture

作者： J. M. Mulder R. J. Portier A. Srivastava R. in't Velt Section Digital Systelns and Computer Architecture Department of Electrical Engineering Delft University of Technology POBox 5031260O AG Delft The Netherlands

ISBN: (纸本)9780897913195

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each *** SCalable ARChitecture Experiment (SCARCE) aims to provide a framework for application-specific processor design. The framework allows scaling of functionality, implementation complexity, and performance. The SCARCE framework consists and will consist of: an architecture framework defining the constraints for the design of application-specific architectures; tools for synthesizing architectures from application or application-area; VLSI cell libraries and tools for quick generation of application-specific processors; a system-software platform which can be retargeted quickly to fit the application-specific architecture;This paper concentrates primarily on the architecture framework of SCARCE, but also presents briefly some software issues and outlines the process of generating VLSI processors.

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Efficient macro-code emulation in hardwired pipelined processors 21

Efficient macro-code emulation in hardwired pipelined proces...

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Proceedings of the 21st annual workshop on Microprogramming and microarchitecture

作者： J. M. Mulder R. J. Portier A. Srivastava R. in't Velt Section Digital Systems and Computer Architecture Department of Electrical Engineering Delft University of Technology POBox 5031 2600 AG Delft The Netherlands

ISBN: (纸本)9780818619199

Traditionally microcoded computers have been the ideal machines for implementing scalable architectures. These machines easily implement application-specific functionality in microcode and they allow architecturally transparent variation of cost/performance by trading off application code, microcode, and hardware. In contrast, hardwired machines are intrinsically incapable of implementing scalability, because they only implement a single level of interpretation. Recent RISC designs have introduced architectural features which partly resolve the scalability issues. They implement architectural openendness to allow application-specific functionality to be added to the architecture (by means of coprocessors and special function units). Additionally they define functions which, depending on application, cost, and performance, can be implemented in hardware or, by means of emulation, in *** identical from an abstract point of view, scalability by means of microprogramming and by means of emulation on a hardwired machine is significantly different. This paper describes the emulation facility provided in SCARCE (SCalable ARChitecture Experiment), a streamlined architecture specifically designed for a wide range of embedded applications, requiring high performance. While architecturally transparent, this emulation facility operates with little overhead (8 cycles), adds three control registers, and is always interruptible. By increasing the hardware investment, the overhead could be decreased to 4 cycles per trap.

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