In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are insert...
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In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). A framework is described that uses an object-oriented approach to transform a given dataflow graph and to generate code for the actors as well as for the interfaces. The object-orientation enables an easy migration (retargeting) of typical communication primitives to other target architectures.
A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the...
A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the optimal schedule of regular algorithms with and without resource constraints, (2) the class of algorithms is extended by allowing certain non-convex index domains, (3) efficient branch and bound techniques are used such that problems of relevant size can be solved. Moreover, additional constraints such as cache memory, bus bandwidths and access conflicts can be considered also. The results are applied to an example of relevant size.
An approach to system-level modeling and simulation of a class of heterogeneous real-time systems the timing behaviour of which can be modeled by deterministic discrete event systems is described. Examples of systems ...
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An approach to system-level modeling and simulation of a class of heterogeneous real-time systems the timing behaviour of which can be modeled by deterministic discrete event systems is described. Examples of systems we consider are self-timed systems, synchronously clocked systems, and mixed asynchronous/synchronous systems. Our model is based on several extensions to the model of timed marked graphs. Basically, we augment this model by adding new schedule constraints such that we can express simultaneity, synchronicity, finite buffering as well as arbitrary combinations of min- and max-constraints. We prove that these extensions allow efficient timing analysis and we show how to simulate realistic systems using the Ptolemy design system.
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