检索结果-内蒙古大学图书馆

SYSTEMS AND computerS IN JAPAN 1995年第7期26卷 1-12页

作者： FUJIWARA, E TANAKA, T Member Faculty of Engineering Tokyo Institute of Technology Tokyo Japan 152 Eui Fujiwara:received his B.S. and M.S. degrees in Electronics Engineering in 1968 and 1970 respectively and his Dr. of Eng. degree in 1981 all from Tokyo Institute of Technology. In 1970 he joined the NTT Musashino Electrical Communication Laboratories and engaged in developing PIPS-1 and PIPS-11 computer systems. In 1988 he joined the Department of Computer Science Tokyo Institute of Technology as an Associate Professor. In 1990 he became a full Professor. He was a Visiting Professor at the Center for Advanced Computer Studies the University of Southwestern Louisiana from June 1985 to July 1986. His current research interests include coding theory for computers fault-tolerant memories VLSI defect-toleranceand WSI systems. He is a co-author ofError Control Coding for Computer Systems(Prentice-Hall1989) EssentiaLF of Error-Correcting Coding Techniques (Academic Press 1990) and other books. Dr. Fujiwara received the Young Engineer Award from the I.E.I.C.E. in 1978 and the Teshima Memorial Research Award in 1991. He is a senior member of the IEEE and a member of the Information Processing Society Japan. Associate Member

Because of its capability of high-speed search, the associative memory (CAM) is expected to be used in a variety of information processing systems. In this paper, novel fault-tolerant techniques which are effective for on-line use are proposed for TLB which is an example of the application of CAM. First, fault and error models of the TLB consisting of the CAM part and the SRAM part are clarified. Then, the fault-tolerant techniques for these faults and errors, such as distance separable technique, cod-ing technique, simplified 1-out-of-n check and graceful degradation, are proposed. The distance separable technique which encodes the data stored in the CAM part is the one which masks the faulty CAM part and prevents errors from propagating to the subsequent circuits. The coding technique checks the one-to-one correspondence between the data in the CAM and those in SRAM by using the SEC-DED code with byte error detection capability, i.e., SEC-DED-SbED code, and at the same time it detects and corrects errors in the data stored in SRAM. The simplified 1-out-of-n check processes association errors. The graceful degradation gives a flag in the faulty memory section and prevents it from being used. The methods proposed in this paper are evaluated from area augmentation and error detection capability perspectives. The results show that the fault-tolerant TLB with 32 virtual address bits, 32 physical address bits and 128 entries gives single fault detection probability of nearly 99 percent with 28 percent area increase.

关键词： CAM TLB DISTANCE SEPARABLE TECHNIQUE CODING TECHNIQUE SIMPLIFIED 1-OUT-OF-N CHECK GRACEFUL DEGRADATION

来源：评论

学校读者我要写书评

暂无评论

Testing combinational iterative logic arrays for realistic faults

Testing combinational iterative logic arrays for realistic f...

引用

VLSI Test Symposium

作者： D. Gizopoulos D. Nikolos A. Paschalis Institute of Informatics & Telecomm National Centre for Scientific Research Attica Greece Department of Computer Engineering & Informatics University슠of슠Patras Patras Greece

In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear-testability are preserved. According to our approach the extensive work made for ILAs under the Cell Fault Model can be easily used to derive an efficient test set of an ILA for more realistic faults.

关键词： Logic testing Logic arrays Sequential analysis Libraries informatics Sufficient conditions Telecommunication computing Very large scale integration Design automation Delay

来源：评论

学校读者我要写书评

暂无评论

A Two-level distributed detection algorithm of AND/OR deadlocks

引用

Journal of Parallel and Distributed Computing 1995年第2期28.0卷 149-161页

作者： Ryang, Dal-Soo Park, Kyu Ho Information Technology R and D Laboratory GoldStar Company Seoul 137-140 16 Woomyeon-dong Seocho-gu South Korea Computer Engineering Research Laboratory Department of Electrical Engineering Korea Advanced Institute of Science and Technology Taejeon 305-701 373-1 Kusung-dong Yusung-gu South Korea

Numerous algorithms on distributed deadlock detection in distributed systems have been proposed for various deadlock models such as the AND model, OR model, and AND/OR model. This paper describes a new distributed algorithm for the AND/OR model by two levels of deadlock detection procedures. In every deadlock model, the existence of a cycle in a wait-for graph is a necessary condition. At the first level of our algorithm, a wait-for cycle is detected with a very simple operation. If no cycle is found, a deadlock does not exist. In this level, deadlocks consisting of AND-requested nodes are detected, and for the cycle of AND- and OR-requested nodes, an initiator is elected and the second-level algorithm is initiated by the initiator. The second-level algorithm uses the deadlock detection method of Herman and Chandy, but the communication cost is reduced even in the worst case because the second-level operation can be initiated by only qualified initiators. © 1995 academic Press, Inc.

关键词：

来源：评论

学校读者我要写书评

暂无评论

An efficient comparative concurrent Built-In Self-Test technique

An efficient comparative concurrent Built-In Self-Test techn...

引用

Asian Test Symposium (ATS)

作者： I. Voyiatzis D. Nikolos A. Paschalis C. Halatsis T. Haniotakis Institute of Informatics and Telecommunications National Centre for Scientific Research Attiki Greece Department of Computer Engineering and Informatics University of Patras Patra Greece Department of Informatics University of Athens (NKUA) Athens Greece

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides for off-line test generation, when it is desirable, and thus accomplishes a mixed on-line/off-line BIST scheme. However, in C-BIST when the test sequence is long, the time required for all the test vectors to appear among the normal inputs to the circuit (test latency) is significantly long. Modifications of the C-BIST technique have been proposed in order to reduce the test latency. In this paper we propose a new C-BIST technique termed windowed-CBIST (w-CBIST) for test latency reduction. The proposed technique is shown to be significantly more efficient from the previous methods with respect to test latency and hardware overhead.

关键词： Automatic testing Circuit testing Built-in self-test Delay Very large scale integration informatics System testing Electrical fault detection Fault detection Circuit faults

来源：评论

学校读者我要写书评

暂无评论

An optimal algorithm for Monte Carlo estimation

An optimal algorithm for Monte Carlo estimation

引用

Annual IEEE Symposium on Foundations of computer Science

作者： P. Dagum R. Karp M. Luby S. Ross Section on Medical Informatics Rockwell Palo Alto Laboratory Stanford University School of Medicine Palo Alto CA USA Computer Science Division University of California Berkeley USA International Computer Science Institute Berkeley CA USA Department of Industrial Engineering and Operations Research University of California Berkeley USA

A typical approach to estimate an unknown quantity /spl mu/ is to design an experiment that produces a random variable Z distributed in [O,1] with E[Z]=/spl mu/, run this experiment independently a number of times and use the average of the outcomes as the estimate. In this paper, we consider the case when no a priori information about Z is known except that is distributed in [0,1]. We describe an approximation algorithm AA which, given /spl epsiv/ and /spl delta/, when running independent experiments with respect to any Z, produces an estimate that is within a factor 1+/spl epsiv/ of /spl mu/ with probability at least 1-/spl delta/. We prove that the expected number of experiments ran by AA (which depends on Z) is optimal to within a constant factor for every Z.

关键词： Monte Carlo methods Approximation algorithms Estimation theory Silicon compounds computer science Upper bound Algorithm design and analysis Random variables Probability Design for experiments

来源：评论

学校读者我要写书评

暂无评论

PARALLEL AND DISTRIBUTED TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETIC-FIELD MODELING

引用

INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

来源：评论

学校读者我要写书评

暂无评论

Undersea technologies in the former Soviet Union

引用

NAVAL ENGINEERS JOURNAL 1995年第6期107卷 85-92页

作者： DeHaemer, DJ Dr. Michael J. DeHaemer:is Director of the World Technology Evaluation Center and the Japanese Technology Evaluation Center at Loyola College in Baltimore. He has directed more than a dozen studies of technologies in foreign countries under the sponsorship of the National Science Foundation ARPA Departments of Energy and Commerce and other agencies. He has a continuing interest in assessing foreign technologies in comparison to the United States.—-On the faculty of the Sellinger School of Business at Loyola College Dr. DeHaemer is a former department chairman and an associate professor of information systems and decision sciences. He teaches the strategic use of information technology and human-computer interface design. His research includes user performance with automated speech recognition systems for computers and business applications of artificial intelligence. Dr. DeHaemer completed an earlier career as a submarine officer including command of a ballistic missile submarine. He holds a B.S. degree from the University of Notre Dame and a Master's degree in Operations Analysis from the Naval Postgraduate School. He has an M.B.A. an M.S. in Industrial Engineering and a Ph.D. in Management Information Systems from Rensselaer Polytechnic Institute.

A team of experts, assembled by the World technology Evaluation Center, visited twenty-five locations in Russia and Ukraine to observe the state of undersea technologies. academic sites, basic research institutes, industrial development laboratories, and oceanographic operating bases were visited. The report highlights specific technologies that support research submersibles;and critiques the strengths and weaknesses of the ocean technologies establishment. Russia and Ukraine were found to have a number of strengths, especially in test facilities, a large fleet of surface and submersible research vessels, and highly educated and qualified engineers and scientists. Although political and economic conditions need to be over-come, there is motivation for many cooperative commercial or research ventures with both government institutes and new private companies in Russia and Ukraine.

关键词： Ocean engineering

来源：评论

学校读者我要写书评

暂无评论

On the testability of purely recursive digital filters 6th

引用

6th International Conference on Parallel Architectures and Languages Europe, PARLE 1994

作者： Vergis, Anastasios Verykios, Vassilios Department of Computer Engineering and Informatics University of Patras Patras26500 Greece Computer Technology Institute of Greece Greece

ISBN: (纸本)9783540581840

This paper presents a method for generating tests for purely recursive digital filters. Generally, these consist of modules such as adders, multipliers and memory elements that are interconnected to realize complex functions. Our approach uses regular propagating test sequences that deal with the inherent parallel form of these structures. We derive a test sequence for the application of test vectors from a predetermined single-cell test set to all the cells of an Nth order filter. Reduced testing time is achieved by using pipelining in vector application. A full speed test sequence is considered with a minimal number of test vectors. © Springer-Verlag Berlin Heidelberg 1994.

关键词： Bandpass filters

来源：评论

学校读者我要写书评

暂无评论

Design and implementation of a high-performance, modular, sorting engine

Design and implementation of a high-performance, modular, so...

引用

European Design and Test (ED&TC) Conference

作者： G. Alexiou D. Stiliadis N. Kanopoulos Department of Computer Engineering and Informatics University of Patras Patras Greece Center for Digital Systems Engineering Research and Triangle Institute NC USA

This paper presents the design and implementation of a modular, expandable and high-performance sorter based on the rebound sorting algorithm. This single chip rebound sorter can sort 24, 32-bit or 64-bit records of 2's complement or unsigned data in either ascending or descending order. The modular design of the sorter allows direct cascading of chips for sorting more than 24 records. The monolithic sorter is implemented in 2.0 /spl mu/m CMOS technology, in a frame of 7.9 mm/spl times/9.2 mm, which supports its 84 I/O. A pipelining scheme was used to achieve a sustained throughput (of cascaded sorting chips) of 10 MHz, while a scan-path was used to allow external control of memory elements for testing purposes. The design of the sorter reported in this paper is a significant improvement in terms of functionality, versatility and performance, over previously reported monolithic sorter circuits.< >

关键词： Sorting Engines Algorithm design and analysis CMOS technology Throughput Circuits Silicon informatics Digital systems Systems engineering and theory

来源：评论

学校读者我要写书评

暂无评论

C-testable multipliers based on the modified Booth algorithm

C-testable multipliers based on the modified Booth algorithm

引用

Asian Test Symposium (ATS)

作者： D. Gizopoulos D. Nikolos A. Paschalis P. Kostarakis Institute Informatics & Telecommunications National Centre for Scientific Research Attiki Greece Department Computer Engineering & Informatics University슠of슠Patras Patra Greece

In this paper we show that the conventional implementation of the multiplier based on the modified Booth algorithm with 2-bit recording is not C-testable and then we propose simple modifications that result in a C-testable design. A test set of 80 vectors is sufficient to test each cell of our multiplier exhaustively, irrespectively of its size. All single stuck-at faults are detectable with only 31 test vectors. The number of the required extra primary inputs is only two, while both the hardware and delay overhead are very small and decrease with increasing N. For example, for our C-testable design of the 64/spl times/64 multiplier, the hardware overhead is 1.60% and the delay overhead is 9.76%.< >

关键词： Circuit testing Circuit faults Delay Very large scale integration Hardware Logic arrays Electrical fault detection Fault detection informatics Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：