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Offering open hypermedia services to the WWW: A step-by-step approach for developers 03

Offering open hypermedia services to the WWW: A step-by-step...

引用

12th International Conference on World Wide Web, WWW 2003

作者： Karousos, Nikos Pandis, Ippokratis Reich, Siegfried Tzagarakis, Manolis Research Academic Computer Technology Institute 26500 Rion Greece Dept. of Computer Engineering and Informatics University of Patras 26500 Rion Greece Salzburg Research Austria

ISBN: (纸本)1581136803

Hypermedia systems and more specifically open hypermedia systems (OHS) provide a rich set of implementations of different hypertext flavors such as navigational hypertext, spatial hypertext or taxonomic hypertext. Additionally, these systems offer component-based modular architectures and address interoperability between hypertext domains. Despite multiple efforts of integrating Web clients, a widespread adoption of OHS technology by Web developers has not taken place. In this paper it is argued that Web Services - which offer a component model for Web applications - can be integrated in OHSs. An architectural integration is proposed, a step-by-step process is outlined and an example of integration is provided. This very approach is aimed to benefit both worlds: the Web community with new rich hypermedia functionality that extends the current navigational hypermedia, and the OHS community by opening its tools and platforms to the many developer groups of the Web community.

关键词： Hypermedia systems

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A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders

A systematic methodology for designing area-time efficient p...

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Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

作者： Dimitrakopoulos, G. Vergos, H.T. Nikolas, D. Efstathiou, C. Computer Engineering Dept. University of Patras 26500 Patras Greece Computer Technology Institute 3 Kolokotroni Str. 26221 Patras Greece Informatics Dept. TEI of Athens Ag. Spyridonos St. 12210 Egaleo Athens Greece

In this paper a systematic methodology for designing parallel-prefix modulo 2n - 1 adders, for every n, is introduced. The resulting modulo 2n - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims to the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area × time complexity reduction of up to 46% when compared to previously reported designs.

关键词： Adders

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Efficient BIST schemes for RNS datapaths

Efficient BIST schemes for RNS datapaths

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Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

作者： Nikolas, D.G. Nikolas, D. Vergos, H.T. Efstathiou, C. Computer Engineering Dept. University of Patras 26500 Patras Greece Computer Technology Institute 3 Kolokotroni Str. 26221 Patras Greece Informatics Dept. TEI of Athens Ag. Spyridonos St. 12210 Egaleo Athens Greece

It has recently been shown that accumulators can be used efficiently for test pattern generation as well as for test response compaction. In this paper we present a BIST scheme for accumulators where the accumulator is simultaneously used as a test pattern generator and a response compactor during its own testing. We also show that the proposed BIST scheme is especially suitable for accumulator, adder and multiplier-accumulator RNS channels leading to minimal hardware overhead and short test sequences.

关键词： Integrated circuits

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An information hiding method based on computational intractable problems

引用

8th Panhellenic Conference on informatics, PCI 2001

作者： Armeni, Spyridoula M. Christodoulakis, Dimitris N. Kostopoulos, Ioannis Kountrias, Polychronis D. Stamatiou, Yannis C. Xenos, Michalis University of Patras Computer Engineering and Informatics Dept Rio Patras26500 Greece Computer Technology Institute 61 Riga Ferraiou Str Patras261 10 Greece Hellenic Open University 16 Sachtouri Str Patras262 23 Greece

ISBN: (纸本)9783540075448

This paper presents an information hiding method that can be used for proving copyright ownership of a digital object. In contrast with other methods, the identity of the owner of the object is proved by the owner’s ability to demonstrate knowledge of a certain property of the signature. The method utilizes Zero Knowledge Interactive Proof (ZKIP) protocols for computationally intractable, or NP-complete, problems and in particular for the 3-coloring problem. This problem requires an assignment of a color out of three available colors to the vertices of a graph so that no two adjacent vertices have the same color. The method prescribes the construction of signatures that represent adjacency matrices of graphs while proof of ownership is effected by knowledge of a 3-coloring by an individual. The computational intractability of the 3-coloring problem implies that knowledge of a coloring of the graph/signature presents sufficient evidence of ownership of any digital file containing this signature. The method has the additional advantage that the disclosure of the signature is of no consequence, since it is essentially the knowledge of the property of the signature (the 3-coloring of the graph it represents) that enables one to use it as proof of ownership of the cover data. The paper focuses on the design of the method and presents experiments from its application on high quality color images. From the experiments it is derived that it is feasible to add the 3-colored graph into color images without affecting image quality (PSNR measurements and HVS examples are presented). More importantly, experiments prove the signature tolerance against various attacks even against attacks that significantly reduce image quality. © Springer-Verlag Berlin Heidelberg 2003.

关键词： Color

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Efficient modulo 2/sup n/+1 tree multipliers for diminished-1 operands

Efficient modulo 2/sup n/+1 tree multipliers for diminished-...

引用

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： C. Efstathiou H.T. Vergos G. Dimitrakopoulos D. Nikolosj Dept. of Informatics TEI of Athens Egaleo Athens Greece Computer Technology Institute Patras Greece Computer Engineering & Informatics Dept. University of Patras Rio Greece

In this work we propose a new method for designing modulo 2/sup n/+l multipliers for diminished-1 operands. Our multipliers compared to the already known tree architecture offer enhanced operation speed for the majority of n values, with similar area complexities. They also have very regular structure, and can be pipelined at the full-adder level.

关键词： Hardware Delay Throughput Costs Bismuth Arithmetic Design methodology

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Virtual-scan: a novel approach for software-based self-testing of microprocessors

Virtual-scan: a novel approach for software-based self-testi...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： G. Dimitrakopoulos X. Kavousianos D. Nikolos Computer Engineering and Informatics Dept. University of Patras Patras Greece Dept. of Computer Science & Technology Univ. of Peloponnese Tripoli Greece Computer Technology Institute Patras Greece

A systematic methodology for generating software-based self-tests for microprocessor cores is introduced in this paper. The produced software tests emulate the functionality of a scan path design, and can be applied during the normal-operation mode of the microprocessor, thus enabling at-speed testing. A major advantage of the proposed approach lies in the fact that the generation of the software tests does not require any knowledge about the low-level implementation of the microprocessor and is only based on its RT-level description and its instruction set architecture.

关键词： Built-in self-test Microprocessors Software testing Automatic testing Circuit testing computer architecture Circuit faults Hardware Scholarships informatics

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A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders

A systematic methodology for designing area-time efficient p...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： G. Dimitrakopoulos H.T. Vergos D. Nikolos C. Efstathiou Computer Engineering and Informatics Dept. University of Patras Patras Greece Computer Technology Institute Patras Greece Informatics Dept. TEI of Athens Egaleo Athens Greece

In this paper a systematic methodology for designing parallel-prefix modulo 2/sup n/ - 1 adders, for every n, is introduced. The resulting modulo 2/sup n/ - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims at the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area /spl times/ time complexity reduction of up to 46% when compared to previously reported designs.

关键词： Design methodology Concurrent computing Adders Application software computer networks informatics Digital arithmetic Fault tolerant systems High-speed networks Proposals

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Test Plan Design for Software Configuration Testing

Test Plan Design for Software Configuration Testing

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Proceedings of the International Conference on Software engineering Research and Practise. SERP 2003

作者： Xu, Baowen Nie, Changhai Shi, Liang Chu, William C. Yang, Hongji Chen, Huowang Dept. of Comp. Sci. and Engineering Southeast University Nanjing 210096 China Jiangsu Inst. of Software Quality Nanjing 210096 China Department of Computer Science TungHai University Taiwan Department of Computer Science De Montfort University United Kingdom College of Computer Science National Univ. of Defense Technology Changsha 410073 China

ISBN: (纸本)193241519X

Configuration testing is an important step in software testing, which is a procedure to test the software with all kinds of hardware to ensure it can run on them. This paper proposes to design configuration testing plan with several common method used in the other fields and analysis their merits, to improve the orthogonal design method with pairwise testing, to decrease the testing risk with multiple factors covering., and presents simple factor cover method which can cover all the factors and pairwise combinations to the greatest degree. All these methods have good merits. At last we make some comparison at the aspects of test suit scale, coverage, usability and etc.

关键词： computer software

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Design optimization for tapered roller bearings using genetic algorithms

Design optimization for tapered roller bearings using geneti...

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Proceedings of the International Conference on Artificial Intelligence, IC-AI 2003

作者： Chaturbhuj, Nandan Nair, S.B. Tiwari, R. Dept. of Computer Science and Eng. Indian Inst. of Technol. Guwahati North Guwahati - 781039 India Dept. of Mechanical Engineering Indian Inst. of Technology Guwahati North Guwahati - 781039 Assam India

ISBN: (纸本)1932415122

The design of tapered roller bearings has a fundamental influence on the performance, life and reliability of the bearings. Consequently, this also affects the operating quality and the economization of machines on which the bearings are used. The responsibility of bearing designers is to select an optimal scheme from all the possible alternative designs, or simply put to make the best choice. A basic requirement for conventional rolling bearings is the maximum dynamic capacity. In this paper we used Genetic Algorithm to search a design for tapered roller bearing, which has maximum dynamic capacity, and the design satisfies all the boundary conditions. The algorithm proceeds with basic objective of increase in dynamic capacity value. At the same time all the constraints are also satisfied.

关键词： Genetic algorithms

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Humanoid Arm Motion Planning using Stereo Vision and RRT Search

Humanoid Arm Motion Planning using Stereo Vision and RRT Sea...

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2003 IEEE/RSJ International Conference on Intelligent Robots and Systems

作者： Kagami, Satoshi Kuffner, James J. Nishiwaki, Koichi Okada, Kei Inaba, Masayuki Inoue, Hirochika Digital Human Lab. Natl. Inst. of Adv. Sci./Technology CREST Program Japan Sci./Technology Corporation School of Computer Science Carnegie Mellon University Dept. of Mechano-Informatics Sch. of Info. Science and Technology Univ. of Tokyo

This paper describes an experimental stereo vision based motion planning system for humanoid robots. The goal is to automatically generate arm trajectories that avoid obstacles in unknown environments from high-level task commands. Our system consists of three components: 1) environment sensing using stereo vision with disparity map generation and online consistency checking, 2) probabilistic mesh modeling in order to accumulate continuous vision input, and 3) motion planning for the robot arm using RRTs (Rapidly exploring Random Trees). We demonstrate results from experiments using an implementation designed for the humanoid robot H7.

关键词： Intelligent robots

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