In this paper a systematic methodology for designing parallel-prefix modulo 2/sup n/ - 1 adders, for every n, is introduced. The resulting modulo 2/sup n/ - 1 adders feature minimum logical depth and bounded fan-out l...
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In this paper a systematic methodology for designing parallel-prefix modulo 2/sup n/ - 1 adders, for every n, is introduced. The resulting modulo 2/sup n/ - 1 adders feature minimum logical depth and bounded fan-out loading. Additionally, an optimization technique is proposed, which aims at the reduction of redundant operators that appear on the parallel-prefix carry computation trees. Performance data reveal that the reduced structures achieve area /spl times/ time complexity reduction of up to 46% when compared to previously reported designs.
Configuration testing is an important step in software testing, which is a procedure to test the software with all kinds of hardware to ensure it can run on them. This paper proposes to design configuration testing pl...
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ISBN:
(纸本)193241519X
Configuration testing is an important step in software testing, which is a procedure to test the software with all kinds of hardware to ensure it can run on them. This paper proposes to design configuration testing plan with several common method used in the other fields and analysis their merits, to improve the orthogonal design method with pairwise testing, to decrease the testing risk with multiple factors covering., and presents simple factor cover method which can cover all the factors and pairwise combinations to the greatest degree. All these methods have good merits. At last we make some comparison at the aspects of test suit scale, coverage, usability and etc.
The design of tapered roller bearings has a fundamental influence on the performance, life and reliability of the bearings. Consequently, this also affects the operating quality and the economization of machines on wh...
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ISBN:
(纸本)1932415122
The design of tapered roller bearings has a fundamental influence on the performance, life and reliability of the bearings. Consequently, this also affects the operating quality and the economization of machines on which the bearings are used. The responsibility of bearing designers is to select an optimal scheme from all the possible alternative designs, or simply put to make the best choice. A basic requirement for conventional rolling bearings is the maximum dynamic capacity. In this paper we used Genetic Algorithm to search a design for tapered roller bearing, which has maximum dynamic capacity, and the design satisfies all the boundary conditions. The algorithm proceeds with basic objective of increase in dynamic capacity value. At the same time all the constraints are also satisfied.
This paper describes an experimental stereo vision based motion planning system for humanoid robots. The goal is to automatically generate arm trajectories that avoid obstacles in unknown environments from high-level ...
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This paper describes an experimental stereo vision based motion planning system for humanoid robots. The goal is to automatically generate arm trajectories that avoid obstacles in unknown environments from high-level task commands. Our system consists of three components: 1) environment sensing using stereo vision with disparity map generation and online consistency checking, 2) probabilistic mesh modeling in order to accumulate continuous vision input, and 3) motion planning for the robot arm using RRTs (Rapidly exploring Random Trees). We demonstrate results from experiments using an implementation designed for the humanoid robot H7.
This paper presents a new two-dimensional (2-D) 8×8 discrete cosine/inverse discrete cosine transform (DCT/IDCT) core design using the group distributed arithmetic (GDA) approach. We adopt the way of DA computati...
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This paper presents a new two-dimensional (2-D) 8×8 discrete cosine/inverse discrete cosine transform (DCT/IDCT) core design using the group distributed arithmetic (GDA) approach. We adopt the way of DA computation and exploit the good features of the cyclic convolution to facilitate an efficient realization of 2-D 8×8 DCT/IDCT core design using shared ROM modules, barrier shifters, and accumulators. To increase the ROM utilization, we re-arrange the content of ROM into several groups in which all the elements in a group will be accessed simultaneously in accumulating the DCT/IDCT outputs. The comparison results with the existing designs show that the proposed design possesses averagely 62.6 % reduction in the delay-area products (ns*Kμm2) based on a 0.35μm CMOS technology.
The problem of cooperatively performing a collection of tasks in a decentralized setting where the computing medium is subject to adversarial perturbations is one of the fundamental problems in distributed computing. ...
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ISBN:
(纸本)1581136048
The problem of cooperatively performing a collection of tasks in a decentralized setting where the computing medium is subject to adversarial perturbations is one of the fundamental problems in distributed computing. Such perturbations can be caused by processor failures, unpredictable delays, and communication breakdowns. To develop efficient distributed solutions for computation problems ranging from distributed search such as SETI to parallel simulation and multi-agent collaboration, it is important to understand efficiency trade-offs characterizing the ability of p processors to cooperate on t-tasks in the presence of adversity. This paper surveys recent results grouped by the following topics: (i) failure-sensitive bounds for distributed cooperation problems for synchronous processors subject to crash failures, (ii) bounds on redundant work for distributed cooperation when individual asynchronous processors may experience prolonged absence of communication, and (in) competitive analysis of cooperative work performed by groups of asynchronous processors, when the groups may be fragmented and merged during the computation. These research results are motivated by the earlier work of the third author with Paris C. Kanellakis at Brown University.
This paper proposes a simple control method to improve the ignition behavior of cold cathode fluorescent lamp in digital-dimming control. The half-bridge resonant inverter is employed in the presented backlight system...
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This paper proposes a simple control method to improve the ignition behavior of cold cathode fluorescent lamp in digital-dimming control. The half-bridge resonant inverter is employed in the presented backlight system. To extend the lamp life, we realize a digital-dimming controller with soft-starting technique (DDC-SST) to reduce the high ignition voltage and to eliminate the ignition current spike. Complete analysis and design considerations are discussed in detail in this paper. Simulation and experimental results are close to the theoretical prediction. The overall efficiency of the system achieved at the rated power is over 91%. The ignition voltage is reduced about 30% without any lamp current spike occurred under digital-dimming operation.
This paper proposes an on-demand distributed clustering algorithm for self-organizing, multihop, mobile packet radio network where mobile nodes are organized into nonoverlapping clusters. These clusters are independen...
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ISBN:
(纸本)0889863741
This paper proposes an on-demand distributed clustering algorithm for self-organizing, multihop, mobile packet radio network where mobile nodes are organized into nonoverlapping clusters. These clusters are independently controlled and are dynamically reconfigured as nodes may move from one cluster to another cluster. The main advantages of network are to provide spatial reuse of bandwidth due to node clustering and to share or reuse bandwidth in a controlled fashion in each cluster. The proposed algorithm is robust due to the motion, failure, insertion or deletion of nodes. This non periodic algorithm for clusterhead election reduces the computational cost and communication costs.
In SoC design, synchronous buses are used frequently to interconnect several IPs. However, it is difficult to use synchronous buses for SoC design because of the increase of wire delay caused by the crosstalk effect a...
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In SoC design, synchronous buses are used frequently to interconnect several IPs. However, it is difficult to use synchronous buses for SoC design because of the increase of wire delay caused by the crosstalk effect and the difficulty of synchronisation caused by the clock-skew problem. The use of an asynchronous bus is an alternative solution for SoC design methodology. A new handshake protocol is proposed using the return-to-zero data encoding scheme for the implementation of a new high performance asynchronous bus. Simulation results reveal that the proposed handshake protocol increases the read throughput of the asynchronous bus by 30.5%, and decreases the read latency by 12.5%.
We propose an algorithm for finding the optimal decoder activation order in a system with more than two concatenated codes. Optimality is defined as the order that yields convergence using the lowest computational com...
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We propose an algorithm for finding the optimal decoder activation order in a system with more than two concatenated codes. Optimality is defined as the order that yields convergence using the lowest computational complexity, guided by the extrinsic information transfer (EXIT) charts of the component codes. We also describe how the convergence threshold for the system can be visualized by combining several multi-dimensional EXIT charts into one two-dimensional EXIT chart.
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