In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are automa...
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In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are automatically inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). An object-oriented approach is presented that enables an easy migration (retargeting) of typical communication primitives to other target architectures.
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are insert...
详细信息
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/software architectures is treated. Starting with a given hardware/software partition, interfaces are inserted into the specification to account for communication, in particular across hardware/software boundaries. Depending on the target architecture, the interfaces are refined according to given communication constraints (bus protocols, memory mapping, interrupts, DMA, etc.). A framework is described that uses an object-oriented approach to transform a given dataflow graph and to generate code for the actors as well as for the interfaces. The object-orientation enables an easy migration (retargeting) of typical communication primitives to other target architectures.
The purpose of the paper is to describe a new semi-automated design space exploration method based on genetic programming. A new control/dataflow specification method is proposed as well as appropriate models for hard...
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The purpose of the paper is to describe a new semi-automated design space exploration method based on genetic programming. A new control/dataflow specification method is proposed as well as appropriate models for hardware parts and algorithms. With this method we are able to test many different hardware architectures and algorithms against cost, speed, computation time and other constraints within a very short time. The remaining manual work is to exploit the model parameters of the components of the architecture and the algorithm. In contrast to other approaches our method is suited for embedded and distributed systems. The method, models and application are explained in detail by means of a comprehensive case study.
Cooperative software engineering typically involves many actors and resources that cooperate in a complex distributed and heterogeneous world. In the DIPS (Distributed Integrated Process Services) project, a 3D model ...
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Cooperative software engineering typically involves many actors and resources that cooperate in a complex distributed and heterogeneous world. In the DIPS (Distributed Integrated Process Services) project, a 3D model is used for the definition, enactment and tracing of software development processes, which expresses both the structure and evolution of such processes. This paper discusses how an optimal architecture was evaluated to implement the process model in a process support framework. Process-specific and general requirements are identified, and expected usage patterns of a DIPS-based environment are analyzed. A set of potential architecture variants is proposed, and implications of the requirements and usage patterns on the variants are discussed qualitatively. An evaluation of the architecture alternatives leads to the design of a hybrid DIPS architecture based on distributed heterogeneous objects. The prototype DIPS implementation is briefly outlined.
The aim of this work was to develop a procedure that allows prosodic modifications of speech signals without impairing the quality. The developed procedure is based on the Fourier analysis/synthesis technique with sev...
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ISBN:
(纸本)0780335554
The aim of this work was to develop a procedure that allows prosodic modifications of speech signals without impairing the quality. The developed procedure is based on the Fourier analysis/synthesis technique with several improvements on the analysis side, such as the analysis of signals with rapidly changing F-0 and the analysis of weak spectral components. Also for the modification of the short-time spectrum and for the reconstruction of the speech signal some new methods have been introduced. The most important one, in terms of speech quality, is the way of phase compensation that limits the absolute time shift to half the pitch period. The developed procedure is used in our high-quality text-to-speech synthesis system that is based on concatenation of prosodically modified diphones.
A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the...
A method for optimizing the schedule and allocation of uniform algorithms onto processor arrays is derived. The main results described in the following paper are: (1) single (integer) linear programs are given for the optimal schedule of regular algorithms with and without resource constraints, (2) the class of algorithms is extended by allowing certain non-convex index domains, (3) efficient branch and bound techniques are used such that problems of relevant size can be solved. Moreover, additional constraints such as cache memory, bus bandwidths and access conflicts can be considered also. The results are applied to an example of relevant size.
An approach to system-level modeling and simulation of a class of heterogeneous real-time systems the timing behaviour of which can be modeled by deterministic discrete event systems is described. Examples of systems ...
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An approach to system-level modeling and simulation of a class of heterogeneous real-time systems the timing behaviour of which can be modeled by deterministic discrete event systems is described. Examples of systems we consider are self-timed systems, synchronously clocked systems, and mixed asynchronous/synchronous systems. Our model is based on several extensions to the model of timed marked graphs. Basically, we augment this model by adding new schedule constraints such that we can express simultaneity, synchronicity, finite buffering as well as arbitrary combinations of min- and max-constraints. We prove that these extensions allow efficient timing analysis and we show how to simulate realistic systems using the Ptolemy design system.
In this paper a new approach for detecting and estimating chirp signals is presented. Based upon the state space representation method of circuits and systems, a three-point non-linear recursive equation, which descri...
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This volume of the Lecture Notes in computer Science series contains the set of papers accepted for publication at the colocated QofIS/ICQT 2002 workshops, i.e. the 3rd COST Action 263 International Workshop on Qualit...
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ISBN:
(数字)9783540458593
ISBN:
(纸本)9783540443568
This volume of the Lecture Notes in computer Science series contains the set of papers accepted for publication at the colocated QofIS/ICQT 2002 workshops, i.e. the 3rd COST Action 263 International Workshop on Quality of future Internet Services (QofIS) and the 2nd International Workshop on Internet Charging and QoS Technology (ICQT), both of which took place at the ETH Zric h, Switzerland, hosted by the computerengineering and Networking laboratory, TIK. QofIS 2002 was the third in a series of highly successful technical workshops and meetings on Internet services within the framework of the COST Action 263 Q uality of future Internet Services , following previous events in Berlin, Germany in 2000 and in Coimbra, Portugal in 2001. ICQT 2002 was the follow-up to a vivid and extremely well-attended workshop on Internet economics and charging technology that took place within the framework of the Annual Meeting of the German Society for computer Science (GI) and the Austrian computer Society in 2001 in Vienna, Austria.
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