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6th International Conference on real-time Computing systems and Applications, RTCSA 1999

作者： Chen, J. Burns, A. Department of Electrical Engineering National Cheng-Kung University Tainan City 701 Taiwan Real-Time Systems Research Group Department of Computer Science University of York YorkYO10 5DD United Kingdom

ISBN: (纸本)0769503063

The paper presents a timing based approach to implementing fully asynchronous reader/writer mechanisms which addresses the problems of priority inversion and blocking among tasks within multiprocessor real time systems. The approach associates a sequential circular buffer data sharing algorithm, which, although being lock-free and loop-free, is vulnerable to some timing subtlety, with necessary feasibility conditions and a configuring mechanism. Both the feasibility conditions and the configuring mechanism are constructed through analyzing the timing properties of relevant tasks. The feasibility conditions are employed to verify the safety property against a given implementation of the data sharing algorithm while the configuring mechanism helps configure the buffer holding the shared data objects. Applying this timing based approach to the asynchronous data sharing problem has the advantage that sequential data sharing mechanisms may be adapted to help remove priority inversion and blocking incurred by the commonly used lock based synchronization mechanism. Therefore, it demonstrates an effective alternative to the traditional algorithm based approaches. © 1999 IEEE.

关键词： real time systems

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Loop-free asynchronous data sharing in multiprocessor real-time systems based on timing properties

Loop-free asynchronous data sharing in multiprocessor real-t...

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IEEE International Conference on Embedded and real-time Computing systems and Applications (RTCSA)

作者： J. Chen A. Burns Department of Electrical Engineering National Cheng Kung University Tainan Taiwan Real-Time Systems Research Group Department of Computer Science University of York York UK

关键词： real time systems Timing Mechanical factors Processor scheduling Cities and towns Safety Parallel processing Councils Contracts computer science

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Mixed abstraction level hardware synthesis from SDL for rapid prototyping

Mixed abstraction level hardware synthesis from SDL for rapi...

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International Workshop on Rapid System Prototyping (RSP)

作者： O. Bringmann A. Muth F. Slomka W. Rosenstiel G. Farber R. Hofmann Wilhelm-Schickard-Institut für Informatik Department of Computer Engineering Universität Tubingen Germany Laboratory for Process Control and Real-Time Systems Technische Universitä MTünchen Germany Department of Computer Architecture and Performance Evaluation Universität Erlangen Nürnberg Germany

SDL is currently gaining interest as a system level specification language for HW/SW codesign. Automated synthesis of SDL in hardware so far had problems with its efficiency. The investigations on the resource usage of SDL-to-VHDL designs presented in this paper identify two key challenges: minimizing the overhead introduced by SDL process infrastructure, and choosing the appropriate synthesis method. This paper presents a framework for SDL hardware synthesis where VHDL code generation, high-level synthesis and RT-level synthesis are combined. A configurable run-time environment implements services like data handling and message passing in efficient, hand-coded library components, which take into account properties of the target architecture. For these components RT-level synthesis was found to be suitable. The behavior of each SDL process on the other hand is freely specified by the system designer. Depending on the type of application, i.e. complex data-oriented or control-oriented either high-level synthesis, RT-level synthesis, or a combination of both can prove to be optimal.

关键词： Hardware Prototypes Control system synthesis Timing High level synthesis computer architecture Resource management Arithmetic High performance computing Design engineering

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Non-Preemptive Scheduling to Maximize the Minimum Global Inter-Completion time (MGICT) 1

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IFAC Proceedings Volumes 1998年第14期31卷 135-140页

作者： Carlos C. Amaro Sanjoy K. Baruah Alexander D. Stoyen Wolfgang A. Halang Dependable Real- Time Systems Laboratory Department of Computer & Information Science New Jersey Institute of Technology University Heights Newark NJ 07102 USA Department of Computer Science The University of Vermont Burlington VT 05405 Faculty of Electrical Engineering Fernuniversität 58084 Hagen Germany

Temporal load-balancing - "spreading out" the executions of tasks over time - is desirable in many applications. A form of temporal load-balancing is discussed: scheduling to maximize minimum global inter-completion time (MGICT-scheduling). It is shown that MGICT-scheduling is, in general, NP-hard. A number of restricted classes of task systems are identified, which can be efficiently MGICT-scheduled.

关键词： non-preemptive scheduling independent tasks multiple processors loadbalancing

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Load adjustment and filtering based on process criticality

Load adjustment and filtering based on process criticality

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IEEE International Conference on Embedded and real-time Computing systems and Applications (RTCSA)

作者： Tei-Wei Kuo Shie-Kai Ni Giun-Haur Huang Real Time Systems Laboratory Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan Department of New Technology Development Platform Software Division Acer Incorporated Taipei Taiwan System Software Laboratory Institute for Information Industry Taipei Taiwan

ISBN: (纸本)081869209X

This paper generalizes the load scaling techniques proposed in (Kuo and Mok, 1991) for fixed-priority real-time applications. A framework is proposed to adjust the system workload by relating the criticality and flexibility of a process to the resource allocation problem. A load adjustment procedure based on the approximation algorithm (Ni et al., 1997) is proposed to maximize the system profit in an on-line fashion. When the list of allowable configurations is implicitly given by scalable periodic processes, the corresponding load filtering problem is shown to be NP-complete. We also prove the upper bound of the system profit and provide a mechanism to balance the schedulability and the maximum profit of the system.

关键词： Filtering Resource management Job shop scheduling Timing real time systems Approximation algorithms Upper bound Laboratories Frequency computer science

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Scalable hardware priority queue architectures for high-speed packet switches

Scalable hardware priority queue architectures for high-spee...

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3rd IEEE real-time Technology and Applications Symposium

作者： Moon, SW Shin, KG Rexford, J Real-Time Computing Laboratory Dept. of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109 United States Network Mathematics Research Networking and Distributed Systems ATandT Labs Research Murray Hill NJ 07974 United States

ISBN: (纸本)0818680164

In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of priority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper, we first compare four existing hardware priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from Verilog HDL and Epoch implementations.

关键词： computer architecture

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Scalable hardware priority queue architectures for high-speed packet switches

Scalable hardware priority queue architectures for high-spee...

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real-time Technology and Applications Symposium

作者： S.-W. Moon K.G. Shin J. Rexford Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Network Mathematics Research Networking and Distributed Systems AT and T Research Laboratories Murray Hill NJ USA

In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of priority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper we first compare four existing hardware priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from Verilog HDL and Epoch implementations.

关键词： Packet switching Switches Traffic control Scheduling algorithm Asynchronous transfer mode Hardware design languages Communication system traffic control computer architecture Moon real time systems

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On memory protection in real-time OS for small embedded systems

On memory protection in real-time OS for small embedded syst...

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IEEE International Conference on Embedded and real-time Computing systems and Applications (RTCSA)

作者： S. Suzuki K.G. Shin The1st Department of Systems Research Hitachi Research Laboratory Hitachi and Limited Hitachi Ibaraki Japan Real-Time Computing Laboratory Department of Electrical Engineering and Computer University of Michigan Ann Arbor MI USA

Memory protection is an important OS feature for the reliability and safety of real-time control systems. In this paper, we study the feasibility of memory protection in small embedded systems in which memory size ranges from several tens of KBytes to several hundreds of KBytes. We evaluate various protection methods in terms of memory consumption, processing overhead, multiple-thread support, region enlargement, and hardware support. We present a new protection method called intermediate-level skip multi-size paging which skips unused intermediate-level page tables of multi-level paging and supports several page sizes. Our evaluation results show that this method along with paged segmentation and short-circuit segment tree are more cost-effective than other known memory protection methods. Also, the feasibility of intermediate-level skip multi-size paging can be improved if a MMU supporting several page sizes is available for microprocessors.

关键词： Protection real time systems Embedded system Memory management Laboratories Hardware Microprocessors Control systems Kernel computer crashes

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The HIMAC Project: Hierarchical Management and Control in Manufacturing systems

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IFAC Proceedings Volumes 1997年第1期30卷 309-314页

作者： E. Canuto M. Christodoulou c. Chu F. Donati V. Gaganis B. janusz J.M. Proth W. Reithofer M. Vallauri Dipartimento di Automatica e Informatica. Politecnico di Torino. Corso Duca degli Abruzzi 24 1-10129 Torino. Italy Dept. of Electrical & Computer Engineering. Laboratory of Automation Technical University of Crete. GR-73100 Chania (Crete). Greece INRIA Lorraine Technopôle Metz 2000. Rue Marconi 4. F-57070 Metz. France Institute for Real-time Computer Systems and Robotics. University of Karlsruhe Kaiserstrasse 12 D-76128 Karlsruhe. Germany

The paper presents the major features of the ESPRIT Basic Research HIMAC, proposed to the EC after a thorough investigation of the state of the art of manufacturing systems control. HIMAC has followed a new approach, by developing a specific mathematIcs, the Manufactunng Algebra (MA), for modelling and controlling the production processes of discrete manufacturing systems. As a key feature, the MA models can be bottom-up aggregated starting from the very detailed levels used in simulation, thus making poSSIble a coherent model hierarchy at the base of the design and realization of Hierarchical control strategies and architectures. The formulation of the original mathematical approach and its validation criteria are outlined in the paper. For a deeper understanding, the mterested reader can take advantage of the list of references given at the end.

关键词： Manufacturing systems Production control Hierarchical control

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Fast and accurate method to measure interharmonics in power systems

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EUROPEAN TRANSACTIONS ON ELECTRICAL POWER 1996年第3期6卷 169-174页

作者： Dai, X Gretsch, R [?]Associate Prof. Dr.-Ing. Xianzhong Dai (1954) received the Dr. degree (Elec. Eng.) from Tsinghua University of China in 1986. In 1988 he joined Southeast University as Associate Professor. In 1991 he became Humboldt Research Fellow and worked for two years at University of Erlangen-Nurnberg/Germany. His research work is focused to real-time control measurement and computer application on reactive power and harmonics compensation in power systems. (Automatic Control Engineering Department Southeast University Nanjing Jiangsu P. R. China)

In order to improve the resolution of spectrum analysis, the traditional method is to take more sampling periods, e. g. 50 sampling periods corresponding to the spectrum interval of I Hz. This method is not suitable to the interharmonic measurement, because most interharmonics vary rather quickly with the time and so the analysis results based on long time sampling may be useless. In this paper the zero-padding technique with short sampling time is used to resolve interharmonics, and the zoom FFT is used to decrease the computation time in order to meet the needs of real-time measurement. The simulating computation shows that the resolution for two adjacent frequency components is usually sufficient to measure harmonics and interharmonics in power systems with acceptable short sampling and computation time. This method is also suited to analyse harmonics and interharmonics when there exists an undesirable asynchronous deviation between the sampling period and the signal period.

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