For scientists, it is advantageous to use a high level of abstraction for programming their simulations, so that they can focus on the problem at hand instead of struggling with low-level details. However, current HPC...
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ISBN:
(纸本)9781467362399
For scientists, it is advantageous to use a high level of abstraction for programming their simulations, so that they can focus on the problem at hand instead of struggling with low-level details. However, current HPC clusters with multiple GPUs per node only offer explicit communication to and from the GPUs, require manual work to keep the data consistent, and often need explicit kernel programming. Moreover, known GPU programming frameworks are limited to a single GPU or a single machine and also rarely support objects. Our system removes the above restrictions. With a slight but necessary change in Java's semantics, we achieve automatic distribution and efficient use of objects and arrays of objects on multiple GPUs in a cluster. On benchmarks that distribute arrays of objects over five machines with 10 GPUs, we achieve speedups of up to 4.9 compared to one node.
Cyclic codes form an important class of codes. They have very interesting algebraic structure. Furthermore, they are equivalent to many important codes, such as binary Hamming codes, Golay codes and BCH codes. Minimal...
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Cyclic codes form an important class of codes. They have very interesting algebraic structure. Furthermore, they are equivalent to many important codes, such as binary Hamming codes, Golay codes and BCH codes. Minimal codewords in linear codes are widely used in constructing decoding algorithms and studying linear secret sharing scheme. In this paper, we show that in the binary cyclic code all of the codewords are minimal, except 0 and 1. Then, we obtain a result about the number of minimal codewords in the binary cyclic codes.
Fuzzy competition graph as the generalization of competition graph is introduced here. A generalization of fuzzy competition graph known as fuzzy k-competition graph is also defined. These graphs are related to fuzzy ...
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Fuzzy graph is now a very important research area due to its wide application. Fuzzy multigraph and fuzzy planar graphs are two subclasses of fuzzy graph theory. In this paper, we define both of these graphs and studi...
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The Inspector/Executor is well-known for parallelizing loops with irregular access patterns that cannot be analyzed statically. The downsides of existing inspectors are that it is hard to amortize their high run-time ...
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Need and concept of software quality evaluation using artificial neural network (ANN) is described in the article. Architecture and structure of an artificial neural network of quality evaluation have been developed. ...
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ISBN:
(纸本)9781479920976
Need and concept of software quality evaluation using artificial neural network (ANN) is described in the article. Architecture and structure of an artificial neural network of quality evaluation have been developed. The process of ANN training and testing was investigated. Research of ANN functioning results was conducted. ANN on the basis of design stage metrics analysis allows to make a comparative analysis of different projects and choose the best one of the characteristics of complexity and quality.
The aim is reducing IEC 61508 certification effort for safety-related applications. Therefore, an object-oriented middleware has been implemented which, once being SIL3-certified, would allow transferring safety-relat...
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The aim is reducing IEC 61508 certification effort for safety-related applications. Therefore, an object-oriented middleware has been implemented which, once being SIL3-certified, would allow transferring safety-related aspects from the application into an already-certified code layer. Safety-related applications using this middleware then could be written as straightforward as non-safety-related code. The SIL3 middleware is designed for an 8051-based microcontroller. Because of the 8-bit CPU architecture, several limitations have been encountered. These issues are explained in this paper, and solutions are proposed. The middleware will be used on the multi-more safety chip. SIL3 certified multi-core architecture for safety-related applications is described. Also, the SIL3 middleware architecture is given. The middleware is modular. Therefore, if the user does not want to use some modules they will not be included and code footprint will be smaller. In the SIL3 middleware numerous design patterns can be found. Patterns description and purpose are explained. The pseudo code for the singleton pattern is shown. Moreover, module implementation is depicted. The validation of the middleware is presented and the V-model for the middleware is provided. It conforms to the IEC 61508.
In recent years, Pulse Transit Time (PTT) - based non-invasive continuous blood pressure monitoring systems have been investigated extensively. But the most relevant studies did not pay attention to the safety require...
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In recent years, Pulse Transit Time (PTT) - based non-invasive continuous blood pressure monitoring systems have been investigated extensively. But the most relevant studies did not pay attention to the safety requirement of the system. In this paper a method is proposed to model the safety-related system for continuous noninvasive blood pressure monitoring. The V model, 1oo2 system and safe Bluetooth communication are used to enhance the safety of the system.
FPGAs introduce a very attractive platform for the designing process of complex embedded systems. The complexity of these systems should be controlled to fulfill high demands and requirements, especially in safety-rel...
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FPGAs introduce a very attractive platform for the designing process of complex embedded systems. The complexity of these systems should be controlled to fulfill high demands and requirements, especially in safety-related applications, where aspects like reliability, availability and safety are of the utmost significance. In this context, the present paper intends the design and implementation of a novel on-chip quadruple redundant safety-related system architecture (1oo4-architecture - one out of four) as a fault tolerant technique to increase the level of safety integrity, reliability and availability of electronic embedded systems. For this aim the 1oo4-architecture and their related safety characteristics are briefly demonstrated. The FPGA-based embedded system model of this novel architecture is developed and explained. The main part of this paper focuses on the safety-related implementation on FPGA. Finally, an evaluation of the implemented architecture concludes this paper.
In this paper, a concept for a SIL3 middleware implementing safety-related aspects is proposed. The middleware is intended to be used by applications that are written for a recently developed safety system-on-chip. Ea...
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In this paper, a concept for a SIL3 middleware implementing safety-related aspects is proposed. The middleware is intended to be used by applications that are written for a recently developed safety system-on-chip. Each module implements a low-level driver. Each driver represents a specific functionality of the system-on-chip. Once being certified conforming to IEC 61508, the middleware would enable writing safety-related applications aimed at SIL3 almost as straightforward as non-safety-related applications. A multi-core SIL3 architecture for safety-related applications is explained. In addition, possible issues that can arise during the software development are identified. Furthermore, conformance arguments on meeting SIL3 are depicted.
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