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检索条件"机构=Computer Programming"

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Using Shared Arrays in Message-Driven Parallel Programs

Using Shared Arrays in Message-Driven Parallel Programs

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IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Phil Miller Aaron Becker Laxmikant Kale Parallel Programming Laboratory Department of Computer Science University of Illinois Urbana-Champaign USA

This paper describes a safe and efficient combination of the object-based message-driven execution and shared array parallel programming models. In particular, we demonstrate how this combination engenders the composition of loosely coupled parallel modules safely accessing a common shared array. That loose coupling enables both better flexibility in parallel execution and greater ease of implementing multi-physics simulations. As a case study, we describe how the parallelization of a new method for molecular dynamics simulation benefits from both of these advantages. We also describe a system of typed handle objects that embed some of the determinacy constraints of the Multiphase Shared Array programming model in the C++ type system, to catch some violations at compile time. The combined programming model communicates in terms of these handles as a natural means of detecting and preventing errors.

关键词： Arrays Message systems Synchronization Instruction sets Runtime Phased arrays programming

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Unmanned vehicle-aided automated meter reading

Unmanned vehicle-aided automated meter reading

引用

6th International Conference on Broadband Communications and Biomedical Applications, IB2COM 2011

作者： Tuna, Gurkan Gungor, V. Cagri Gulez, Kayhan Trakya University Department of Computer Programming Edirne Turkey Bahçeşehir University Faculty of Engineering Department of Computer Engineering Istanbul Turkey Yildiz Technical University Electrical-Electronics Eng. Faculty Control and Automation Eng. Dept. Istanbul Turkey

ISBN: (纸本)9781467307680

This paper presents a novel approach of using unmanned vehicles for Automated Meter Reading (AMR) applications in rural areas where there are a few consumers scattered around a wide area. The proposed system does not require a fixed network infrastructure to transfer data to a central database, since data collection is carried out by unmanned vehicles. Compared to traditional meter reading systems, the use of unmanned vehicles for AMR brings several advantages, such as low cost operation, flexibility, and online system management. However, the realization of these potential gains directly depends on reliable communication capabilities of the deployed system and successful navigation of unmanned vehicles. Overall, in this paper, the design principles and challenges of using unmanned vehicles for AMR applications in rural areas have been presented. Also, the communication architecture of the proposed system has been explained and comparative simulation studies have been performed in terms of energy efficiency and navigation accuracy. © 2011 IEEE.

关键词： Wireless sensor networks

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Communication related design considerations of WSN-aided Multi-Robot SLAM

Communication related design considerations of WSN-aided Mul...

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IEEE International Conference on Mechatronics

作者： Tuna, Gurkan Gulez, Kayhan Gungor, V. Cagri Trakya University Vocational College of Technical Sciences Department of Computer Programming Edirne Turkey Yildiz Technical University Electrical-Electronics Eng. Faculty Control and Automation Eng. Dept. Istanbul Turkey Bahcesehir University Department of Computer Engineering Besiktas Istanbul Turkey

ISBN: (纸本)9781612849836

This paper presents the communication related design considerations of Wireless Sensor Network (WSN) aided Multi-Robot Simultaneous Localization and Mapping (SLAM). In this approach, multiple robots perform WSN-aided cooperative SLAM using only range values to landmarks in the environment by measuring the Received Signal Strength Indicator (RSSI) of the received radio messages, and odometry information. The SLAM algorithm proposed in this study uses the Rao-Blackwellized Particle Filters. In addition, the inherent communication problems in WSNs, and their effects on cooperative SLAM are explained in detail and shown with the results of The Network Simulator (ns-2) simulations. © 2011 IEEE.

关键词： Wireless sensor networks

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Modelica — A cyber-physical modeling language and the OpenModelica environment

Modelica — A cyber-physical modeling language and the OpenM...

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International Wireless Communications and Mobile Computing Conference, IWCMC

作者： Peter Fritzson PELAB-Programming Environment Laboratory Department Computer Science Linköping University Linkoping Sweden

Modelica is a modern, strongly typed, declarative, equation-based, and object-oriented (EOO) language for modeling and simulation of complex cyber-physical systems. Major features are: ease of use, visual design of models with combination of lego-like predefined model building blocks, ability to define model libraries with reusable components, support for modeling and simulation of complex applications involving parts from several application domains, and many more useful facilities. This paper gives an overview of some aspects of the Modelica language and the OpenModelica environment - the most complete Modelica open-source tool for modeling, simulation, and development of Modelica applications. Special features are MetaModeling for efficient model transformations, the ModelicaML profile for UML-Modelica cyber-physical hardware-software modeling, as well as generation of parallel code for multi-core architectures.

关键词： Mathematical model Unified modeling language Object oriented modeling Equations Computational modeling Rabbits Software

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An OpenCL Framework for Homogeneous Manycores with No Hardware Cache Coherence

An OpenCL Framework for Homogeneous Manycores with No Hardwa...

引用

International Conference on Parallel Architecture and Compilation Techniques (PACT)

作者： Jun Lee Jungwon Kim Junghyun Kim Sangmin Seo Jaejin Lee Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul South Korea

Recently, Intel has introduced a research prototype many core processor called the Single-chip Cloud computer (SCC). The SCC is an experimental processor created by Intel Labs. It contains 48 cores in a single chip and each core has its own L1 and L2 caches without any hardware support for cache coherence. It allows maximum 64GB size of external memory that can be accessed by all cores and each core dynamically maps the external memory into their own address space. In this paper, we introduce the design and implementation of an OpenCL framework (i.e., runtime and compiler) for such many core architectures with no hardware cache coherence. We have found that the OpenCL coherence and consistency model fits well with the SCC architecture. The OpenCL's weak memory consistency model requires relatively small amount of messages and coherence actions to guarantee coherence and consistency between the memory blocks in the SCC. The dynamic memory mapping mechanism enables our framework to preserve the semantics of the buffer object operations in OpenCL with a small overhead. We have implemented the proposed OpenCL runtime and compiler and evaluate their performance on the SCC with OpenCL applications.

关键词： Kernel Runtime Coherence Indexes Arrays Copper

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A Software-Managed Coherent Memory Architecture for Manycores

A Software-Managed Coherent Memory Architecture for Manycore...

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International Conference on Parallel Architecture and Compilation Techniques (PACT)

作者： Jungho Park Choonki Jang Jaejin Lee Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul South Korea

Cache coherent Non-Uniform Memory Access (cc-NUMA) architectures have been widely used for chip multiprocessors (CMPs). However, they require complicated hardware to properly handle the cache coherence problem. Moreover, it generates heavy on-chip network traffic due to the coherence enforcement. In this work, we propose a simple software-managed coherent memory architecture for many cores. Our memory architecture exploits explicitly addressed local stores. Instead of implementing the complicated cache coherence protocol in hardware, coherence and consistency are supported by software, such as a runtime or an operating system. The local stores together with the software leverage conventional caches to make the architecture much simpler and to generate much less network traffic than conventional ccNUMA-based CMPs. Experimental results indicate that our approach is promising.

关键词： Coherence Operating systems System-on-a-chip Memory architecture Runtime

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SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for Manycores

SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynami...

引用

International Conference on Parallel Architecture and Compilation Techniques (PACT)

作者： Sangmin Seo Junghyun Kim Jaejin Lee Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul South Korea

As parallel programming becomes the mainstream due to multicore processors, dynamic memory allocators used in C and C++ can suppress the performance of multi-threaded applications if they are not scalable. In this paper, we present a new dynamic memory allocator for multi-threaded applications. The allocator never uses any synchronization for common cases. It uses only lock-free synchronization mechanisms for uncommon cases. Each thread owns a private heap and handles memory requests on the heap. Our allocator is completely synchronization-free when a thread allocates a memory block and deal locates it by itself. Synchronization-free means that threads do not communicate with each other at all. On the other hand, if a thread allocates a block and another thread frees it, we use a lock-free stack to atomically add it to the owner thread's heap to avoid the memory blowup problem. Furthermore, our allocator exploits various memory block caching mechanisms to reduce the latency of memory management. Freed blocks or intermediate memory chunks are cached hierarchically in each thread's heap and they are used for future memory allocation. We compare the performance and scalability of our allocator to those of well-known existing multi-threaded memory allocators using eight benchmarks. Experimental results on a 48-core AMD system show that our approach achieves better performance than other allocators for all benchmarks and is highly scalable with a large number of threads.

关键词： Instruction sets Resource management Memory management Hazards Synchronization Scalability Data structures

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Performance characterization of the NAS Parallel Benchmarks in OpenCL

Performance characterization of the NAS Parallel Benchmarks ...

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IEEE International Workshop/Symposium on Workload Characterization

作者： Sangmin Seo Gangwon Jo Jaejin Lee Center for Manycore Programming School of Computer Science and Engineering Seoul National University Seoul South Korea

Heterogeneous parallel computing platforms, which are composed of different processors (e.g., CPUs, GPUs, FPGAs, and DSPs), are widening their user base in all computing domains. With this trend, parallel programming models need to achieve portability across different processors as well as high performance with reasonable programming effort. OpenCL (Open Computing Language) is an open standard and emerging parallel programming model to write parallel applications for such heterogeneous platforms. In this paper, we characterize the performance of an OpenCL implementation of the NAS Parallel Benchmark suite (NPB) on a heterogeneous parallel platform that consists of general-purpose CPUs and a GPU. We believe that understanding the performance characteristics of conventional workloads, such as the NPB, with an emerging programming model (i.e., OpenCL) is important for developers and researchers to adopt the programming model. We also compare the performance of the NPB in OpenCL to that of the OpenMP version. We describe the process of implementing the NPB in OpenCL and optimizations applied in our implementation. Experimental results and analysis show that the OpenCL version has different characteristics from the OpenMP version on multicore CPUs and exhibits different performance characteristics depending on different OpenCL compute devices. The results also indicate that the application needs to be rewritten or re-optimized for better performance on a different compute device although OpenCL provides source-code portability.

关键词： Kernel Graphics processing unit Multicore processing Indexes Computational modeling Optimization

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Acculock: Accurate and efficient detection of data races 11

Acculock: Accurate and efficient detection of data races

引用

International Symposium on Code Generation and Optimization (CGO)

作者： Xinwei Xie Jingling Xue Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales NSW Australia

ISBN: (纸本)9781612843568

Happens-before detectors are precise but can be too conservative to detect certain data races in repeated test runs as they are sensitive to thread interleaving. By making the opposite tradeoffs, lockset detectors can detect more races but are not precise (by reporting false positives). For both types of detectors, happens-before detectors run more slowly as they use expensive vector clocks. Existing hybrid race detectors (combining lockset and happens-before) alleviate some of the limitations in both analysis techniques at the cost of additional analysis overhead. Recently, due to FastTrack, epoch-based happens-before and lockset detectors now exhibit comparable performance. It is the time to rethink how to design a hybrid race detector to balance precision and coverage, by leveraging the lightweightness of epoch clocks. Acculock is the first such a solution. Acculock analyzes a program by reasoning about the subset of the happens-before relation observed with lock acquires and releases excluded, thereby reducing its sensitivity to thread interleaving. When such a weaker happens-before relation is violated, Acculock applies a new efficient lockset algorithm to enforce a lock-based synchronization discipline by distinguishing the locks protecting reads and writes. The key motivation behind is to ensure that Acculock can improve happens-before detectors by discovering also data races in alternate thread interleavings when analyzing one program execution while limiting false warnings thus incurred in a controlled manner. In addition, Acculock achieves these objectives by maintaining comparable performance as FastTrack, the fastest happens-before detector. All these properties of Acculock are validated and confirmed by comparing it against six other detectors, all implemented in Jikes RVM using 11 benchmark programs.

关键词： Detectors Clocks Synchronization Instruction sets Copper Algorithm design and analysis

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Fast RNA structure alignment for crossing input structures

Fast RNA structure alignment for crossing input structures

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作者： Backofen, Rolf Landau, Gad M. Möhl, Mathias Tsur, Dekel Weimann, Oren Bioinformatics Institute of Computer Science Albert-Ludwigs-Universität Freiburg Germany Department of Computer Science University of Haifa Haifa 31905 Israel Department of Computer Science and Engineering NYU-Poly Six MetroTech Center Brooklyn NY 11201-3840 United States Programming Systems Lab Saarland University Saarbrücken Germany Ben-Gurion University Beer-Sheva Israel Massachusetts Institute of Technology Cambridge MA 02139 United States

The complexity of pairwise RNA structure alignment depends on the structural restrictions assumed for both the input structures and the computed consensus structure. For arbitrarily crossing input and consensus structures, the problem is NP-hard. For non-crossing consensus structures, Jiang et al.'s (2002) [9] algorithm computes the alignment in O(n2m2) time where n and m denote the lengths of the two input sequences. If the input structures are also non-crossing, the problem corresponds to tree editing which can be solved in O(m2n(1+lognm)) time (Demaine et al., 2007) [3]. We present a new algorithm that solves the problem for d-crossing structures in O(dm2nlogn) time, where d is a parameter that is one for non-crossing structures, bounded by n for crossing structures, and much smaller than n on many practical examples. Crossing input structures allow for applications where the input is not a fixed structure but is given as base-pair probability matrices. © 2010 Elsevier B.V. All rights reserved.

关键词： RNA

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