In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applicati...
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In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications according to the safety standard IEC 61508, meeting the safety integrity level SIL3. Furthermore, a SIL3 operating system and a SIL3 middleware are also briefly presented in this paper. Based on the presented solution, the smallest certified safety controller represents an innovative product and allows system manufacturers to create safe solutions that are ready for certification.
This paper describes the implementation and integration process of a complete communication computer system on the field programmable gate array (FPGA). After such a design is reached, safety measures are integrated t...
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This paper describes the implementation and integration process of a complete communication computer system on the field programmable gate array (FPGA). After such a design is reached, safety measures are integrated to achieve a safety-related architecture. For this purpose a diagnostic unit will be implemented, consisting of hardware and software tests. Hardware tests are related to the control of the FPGA functionality. They are based on the integration of two existing methods to reach complete hardware test coverage. The software tests are used for a continuous testing of the whole system (this means testing the central processing unit, bus systems, peripherals and memory). Furthermore, a safety multiplexer is integrated with the task to turn off the current operating system (main system) and to turn on a redundant system when a failure is introduced via the diagnostic unit. The safety multiplexer has to give the permission to the redundant system to receive the outputs from the main system in a way that is free from faults. The microcontroller ColdFire is used as a basis, which provides numerous features for the control of various peripherals as well as the connection of various types of memory.
Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual compon...
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Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual components of a target control system can be integrated into a single silicon die at lowest level, which in turn contributes in saving the substantial space and reduces power consumption and production costs. With the consideration of the miniaturization of safety-related systems into system-on-chips, where usually complete redundant architectures along with memories and interfaces are integrated into small silicon structures, many advantages can be taken into account. These advantages extend to all levels of the development cycle. In the present paper, a concept for on-chip safety system architecture is presented briefly. Primarily, a qualitative evaluation and analysis of the presented architecture is explicitly focused and discussed. The evaluation and analysis is based on a comparison to a similar conventional discrete safety-related architecture.
In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnost...
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In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnostic units and is designed to meet the highest possible safety integrity level for on-chip systems. The presented on-chip safety system consists of two redundant processor channels, each of which has a processor unit, data memory, program memory, communication interfaces, inputs and outputs. Furthermore, on-chip diagnosis- and monitoring units and a communication core are integrated. The safety-related implementation of the proposed architecture is introduced in this paper. This includes hardware and software implementation methodologies. Finally, a brief evaluation of the presented architecture is presented.
Procedural content generation (PCG) is a research field on the rise, with numerous papers devoted to this topic. This paper presents a PCG method based on a self-adaptive evolution strategy for the automatic generatio...
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Procedural content generation (PCG) is a research field on the rise, with numerous papers devoted to this topic. This paper presents a PCG method based on a self-adaptive evolution strategy for the automatic generation of maps for the real-time strategy (RTS) game Planet Wars. These maps are generated in order to fulfill the aesthetic preferences of the user, as implied by her assessment of a collection of maps used as training set A topological approach is used for the characterization of the maps and their subsequent evaluation: the sphere-of-influence graph (SIG) of each map is built, several graph-theoretic measures are computed on it, and a feature selection method is utilized to determine adequate subsets of measures to capture the class of the map. A multiobjective evolutionary algorithm is subsequently employed to evolve maps, using these feature sets in order to measure distance to good (aesthetic) and bad (non-aesthetic) maps in the training set. The so-obtained results are visually analyzed and compared to the target maps using a Kohonen network.
Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specif...
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Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specific type of memory, it would be straightforward to determine suitable state-of-the-art tests. However, the question our research focuses on is: “Which RAM tests do not need to be performed due to the safety architecture?” Even high-performance tests do require execution time. In the range of safety-related systems, diagnostics may consume most of the central processing unit (CPU) time, depending on the architecture. Therefore, this paper depicts how architectural characteristics can be taken into account to reasonably simplify specific RAM tests. This paper introduces our research on RAM tests in the range of safety-related systems. Therefore, key topics are introduced, first: comprehensively and starting from scratch, thus enabling anyone to follow our research. Second, an example is shown on how detecting stuck-at faults of address and data words, as demanded by IEC 61508 Ed.2.0, can be simplified by taking advantage of a 1oo2D safety architecture.
With the release of the second edition of the standard IEC 61508 for functional safety of electrical, electronic and programmable electronic systems, a set of methodologies and implementation techniques was presented,...
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With the release of the second edition of the standard IEC 61508 for functional safety of electrical, electronic and programmable electronic systems, a set of methodologies and implementation techniques was presented, which allows the realization and certification of safety-related solutions with on-chip redundancy. In a broader context, the standard ISO 26262 offers similar methodologies for safety solutions for automotive applications. The main focus of the research work of our institute is laid on the development and certification of safety-chips according to the standard IEC 61508. Together with an industrial partner, we are developing chip-based safety-related solutions for several industrial applications. In the same context, several semiconductor manufacturers addressed the development of such solutions in the last years, mainly with the focus on automotive applications. The present paper provides an overview of existing and planned safety chip architectures. Furthermore, a cursory analysis of the presented safety-chips is carried out with respect to the standard IEC 61508. A deep qualitative and quantitative analysis require experiments and simulations which will be carried out in future work.
Cardiotocography is one of the most widely used technique for recording changes in fetal heart rate (FHR) and uterine contractions. Assessing cardiotocography is crucial in that it leads to iden- tifying fetuses which...
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Cardiotocography is one of the most widely used technique for recording changes in fetal heart rate (FHR) and uterine contractions. Assessing cardiotocography is crucial in that it leads to iden- tifying fetuses which suffer from lack of oxygen, i.e. hypoxia. This situation is defined as fetal dis- tress and requires fetal intervention in order to prevent fetus death or other neurological disease caused by hypoxia. In this study a computer-based approach for analyzing cardiotocogram in- cluding diagnostic features for discriminating a pathologic fetus. In order to achieve this aim adaptive boosting ensemble of decision trees and various other machine learning algorithms are employed.
Cloud Computing is a new technology that has rapidly established itself in computer science since it allows the usage of huge computing resources that are dynamically allocated in order to satisfy user's needs and...
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Cloud Computing is a new technology that has rapidly established itself in computer science since it allows the usage of huge computing resources that are dynamically allocated in order to satisfy user's needs and that are accessible as a service through a remote interface, such as a web browser. Cloud resources can be distributed in different places and such distribution is made transparent to the user;this one does not need to worry about data replication and/or maintenance of the infrastructure but he/she benefits only of the required services, by exploiting the Pay-Per-Use business model. In this context, the interoperability among different providers becomes critical due to the vendor lock-in problem. Here we present a multi agent system that accesses, on behalf of the user, the utility market of Cloud computing to maintain the best resources configuration that satisfies the application requirements. It also offers management and monitoring facilities for the Cloud infrastructure in order to guide the user in all the phases of the application's lifecycle. Together with the platform, we present client-side tools that can be used to orchestrate agents' based services.
This paper presents an approach of textural signature identification for the classification of high resolution satellite image of forest. We are looking for the most appropriate combination of features from texture me...
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This paper presents an approach of textural signature identification for the classification of high resolution satellite image of forest. We are looking for the most appropriate combination of features from texture measures. This combination which forms our signature should allow the discrimination between different types of textures present in the image that will be classified. We improve our signature by a step of weighting features. The weight of each feature reflects its degree of confidence. We finish with an experimental step which is an application of our combined weighted signature for the purposes of classification of high resolution satellite image of forest.
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