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Science and Information Conference (SAI)

作者： Madhumangal Pal Sovan Samanta Anita Pal Department of Applied Mathematics with Oceanology and Computer Programming Vidyasagar University Midnapore India Department of Mathematics National Institute of Technology Durgapur Durgapur India

Fuzzy competition graph as the generalization of competition graph is introduced here. A generalization of fuzzy competition graph known as fuzzy k-competition graph is also defined. These graphs are related to fuzzy digraphs. Fuzzy neighbourhood graphs, which are related to fuzzy graphs are defined here. Some relations between fuzzy competition graphs and fuzzy neighbourhood graphs have been established. Also several results to find strong edges of the stated graphs are obtained.

关键词： Fuzzy sets Graph theory Environmental factors Biological system modeling Linear algebra Presses

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Comparision of multi-carrier techniques in seven-level asymmetric cascade multilevel inverter

Comparision of multi-carrier techniques in seven-level asymm...

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2013 4th International Conference on Power Engineering, Energy and Electrical Drives, POWERENG 2013

作者： Colak, Ilhami Kabalci, Ersan Keven, Gokhan Faculty of Technology Department of Electric and Electronic Engineering Gazi University Ankara Turkey Faculty of Engineering and Architecture Dep. of Electrical and Electronic Eng. Nevsehir University Nevsehir Turkey Vocational College of Haci Bektaş Veli Dep. of Computer Programming Nevsehir University Nevsehir Turkey

ISBN: (纸本)9781467363921

The multilevel inverters (MLIs) are classified into three topologies such as Diode Clamped, Flying Capacitor and Cascade Multilevel Inverter (CMLI). CMLI topologies include two kind of structure that is named symmetric and asymmetric topologies. Asymmetric Cascade MLI (ACMLI) topologies consist of unequal DC sources. Many modulation techniques have been used in ACMLI topology such as Multi-Carrier PWM (MC-PWM), Space Vector PWM and Selective Harmonic PWM. The MC-PWM technique is achieved by four different types. In this study, MC-PWM techniques which are named Phase Disposition PWM, Phase Opposition Disposition PWM, Alternate Phase Opposition Disposition PWM and Phase Shifted PWM have been compared. It is uncovered that Phase Opposition Disposition PWM technique is more convenient in terms of Total Harmonic Distortion of output voltage and current signals and in terms of the quality of power factor in ACMLI which is performed in this study. © 2013 IEEE.

关键词： Pulse width modulation

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Reliable System Design with a High Degree of Diagnostic Procedures for Embedded Systems

Reliable System Design with a High Degree of Diagnostic Proc...

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IET Irish Signals and Systems Conference

作者： Michael H. Schwarz Josef Boercsoek Department of Safety Computer Technology University of Kassel Department of Computer Architecture and System Programming University of Kassel

ISBN: (纸本)9781629935881

Maintenance starts with reliable diagnostics. programming Logic Controllers (PLCs) are often equipped with a high degree of diagnostic procedures in order to ensure that the processing unit is functioning correctly. It is vital to verify that the system with its programme is still within a 'healthy' state, otherwise a safety function is called and the system is brought into a safe state, or if possible, defect and malfunctioning components are exchanged during operation and the process can continue without shutting down the system. However, when it comes to smaller devices such as intelligent sensors, embedded controller devices with the functionality of an e.g. PID (Proportional-Integral-Derivative), predictive controller, filter or analytical algorithm, which is embedded into a FPGA or micro-controller then diagnostics and verification methods are often not considered in the way they should be. For example, if an intelligent sensor system is not able to diagnose that the sensor-head is malfunctioning, but the sensor-head still provides some data, then the smart algorithm bases its calculation on wrong data, which can cause a dangerous situation. This paper investigates and shows recent results to combine diagnostic methods for small scale devices. Several safety-related structures are considered with a high degree of diagnostic coverage. The paper presents relevant procedures and structures to increase the reliability of small devices without utilising a full scale microcontroller system.

关键词： Reliability Safety structure Maintenance Diagnosis

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PartialRC: A Partial Recomputing Method for Efficient Fault Recovery on GPGPUs

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Journal of computer Science & technology 2012年第2期27卷 240-255页

作者：徐新海杨学军薛京灵林宇斐林一松 National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

GPGPUs are increasingly being used to as performance accelerators for HPC （High Performance Computing） applications in CPU/GPU heterogeneous computing systems, including TianHe-1A, the world＇s fastest supercomputer in the TOP500 list, built at NUDT （National University of Defense technology） last year. However, despite their performance advantages, GPGPUs do not provide built-in fault-tolerant mechanisms to offer reliability guarantees required by many HPC applications. By analyzing the SIMT （single-instruction, multiple-thread） characteristics of programs running on GPGPUs, we have developed PartialRC, a new checkpoint-based compiler-directed partial recomputing method, for achieving efficient fault recovery by leveraging the phenomenal computing power of GPGPUs. In this paper, we introduce our PartialRC method that recovers from errors detected in a code region by partially re-computing the region, describe a checkpoint-based faulttolerance framework developed on PartialRC, and discuss an implementation on the CUDA platform. Validation using a range of representative CUDA programs on NVIDIA GPGPUs against FullRC （a traditional full-recomputing Checkpoint-Rollback-Restart fault recovery method for CPUs） shows that PartialRC reduces significantly the fault recovery overheads incurred by FullRC, by 73.5% when errors occur earlier during execution and 74.6% when errors occur later on average. In addition, PartialRC also reduces error detection overheads incurred by FullRC during fault recovery while incurring negligible performance overheads when no fault happens.

关键词： GPGPU partial recomputing fault tolerance CUDA checkpointing

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Improving performance of all-to-all communication through loop scheduling in PGAS environments 13

Improving performance of all-to-all communication through lo...

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27th ACM International Conference on Supercomputing, ICS 2013

作者： Alvanos, Michail Tanase, Gabriel Farreras, Montse Tiotto, Ettore Amaral, José Nelson Martorell, Xavier Programming Models Barcelona Supercomputer Center Barcelona Spain IBM TJ Watson Research Center Yorktown Heights NY United States Dep. of Computer Architecture Universitat Politècnica de Catalunya Barcelona Spain Static Compilation Technology IBM Toronto Laboratory Toronto ON Canada Dep. of Computing Science University of Alberta Edmonton AB Canada IBM Canada CAS Research Markham ON Canada

No abstract available.

ISBN: (纸本)9781450321303

No abstract available.

关键词： unified parallel c partitioned global address space performance evaluation one-sided communication

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Network virtualization for military application: Review and initial development of conceptual design

Network virtualization for military application: Review and ...

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14th International Conference on Advanced Communication technology, ICACT 2012

作者： Kerdsri, Jiradett Wipusitwarkun, Komwut Computer and Programming Laboratory Defense Technology Institute Thailand Sirindhorn International Institute of Technology Thailand

ISBN: (纸本)9788955191639

Networking technology, undoubtedly, plays a vital role in modern warfare especially in Network Centric Operations (NCOs) and Global Information Grid (GIG) concept. However, the current popular network infrastructure, mainly TCP/IP architecture, is in fact unsuitable with advanced military communication especially in tactical operation networks. The key characteristics of military communications are classified as delay/disruption/disconnection tolerant networks (DTNs) which are long and variable delays, high error rates and greatly heterogeneous. As a result a call for new type of network architecture emerges to support such peculiar characteristics of military communication network. This paper reviews the current approaches in network technology of military communication and proposes the conceptual design of Virtualization Network (VN) for military communication to address the limitation of current network infrastructure. The implementation of Military Network Virtualization Environment (MVNE) introduces the crucial two new key features of military tactical network: information classification and movable nodes. These features along with essential research challenges must be analyzed to realize a viable virtualization network for military communications. © 2012 GIRI.

关键词： Conceptual design

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Improving communication in PGAS environments: Static and dynamic coalescing in UPC 13

Improving communication in PGAS environments: Static and dyn...

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27th ACM International Conference on Supercomputing, ICS 2013

作者： Alvanos, Michail Farreras, Montse Tiotto, Ettore Amaral, José Nelson Martorell, Xavier Programming Models Barcelona Supercomputer Center Barcelona Spain Department of Computer Architecture Universitat Politecnica de Catalunya Cr. Jordi Girona 1-3 08034 Barcelona Spain Static Compilation Technology IBM Toronto Laboratory Toronto ON Canada Dep. of Computing Science University of Alberta Edmonton AB Canada Barcelona Supercomputing Center Cr. Jordi Girona 29 08034 Barcelona Spain IBM Canada CAS Research Markham ON Canada

ISBN: (纸本)9781450321303

The goal of Partitioned Global Address Space (PGAS) languages is to improve programmer productivity in large scale parallel machines. However, PGAS programs may have many fine-grained shared accesses that lead to performance degradation. Manual code transformations or compiler optimizations are required to improve the performance of programs with fine-grained accesses. The downside of manual code transformations is the increased program complexity that hinders programmer productivity. On the other hand, most compiler optimizations of fine-grain accesses require knowledge of physical data mapping and the use of parallel loop constructs. This paper presents an optimization for the Unified Parallel C language that combines compile time (static) and runtime (dynamic) coalescing of shared data, without the knowledge of physical data mapping. Larger messages increase the network efficiency and static coalescing decreases the overhead of library calls. The performance evaluation uses two microbenchmarks and three benchmarks to obtain scaling and absolute performance numbers on up to 32768 cores of a Power 775 machine. Our results show that the compiler transformation results in speedups from 1.15X up to 21X compared with the baseline versions and that they achieve up to 63% the performance of the MPI versions. © 2013 ACM.

关键词： Dynamics

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Comparision of Multi-Carrier Techniques in Seven-Level Asymmetric Cascade Multilevel Inverter

Comparision of Multi-Carrier Techniques in Seven-Level Asymm...

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International Conference on Power Engineering, Energy and Electrical Drives

作者： Ilhami COLAK Ersan KABALCI Gokhan KEVEN Faculty of Technology Department of Electric & Electronic Engineering Gazi University Ankara Turkey Faculty of Engineering & Architecture Dep. of Electrical & Electronic Eng. Nevsehir University Nevsehir Turkey Vocational College of Haci Bekta? Veli Dep. of Computer Programming Nevsehir University Nevsehir Turkey

ISBN: (纸本)9781467363914

关键词： asymmetric cascade multilevel inverter multi carrier PWM THD frequency index power factor

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A Hybrid Circular Queue Method for Iterative Stencil Computations on GPUs

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Journal of computer Science & technology 2012年第1期27卷 57-74页

作者： Yang Yang Hui-Min Cui Xiao-Bing Feng Jing-Ling Xue State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China Graduate University of Chinese Academy of Sciences Beijing 100190China Programming Languages and Compilers Group School of Computer Science and Engineering University of New South WalesSydneyNSW 2052Australia

In this paper, we present a hybrid circular queue method that can significantly boost the performance of stencil computations on GPU by carefully balancing usage of registers and shared-memory. Unlike earlier methods that rely on circular queues predominantly implemented using indirectly addressable shared memory, our hybrid method exploits a new reuse pattern spanning across the multiple time steps in stencil computations so that circular queues can be implemented by both shared memory and registers effectively in a balanced manner. We describe a framework that automatically finds the best placement of data in registers and shared memory in order to maximize the performance of stencil computations. Validation using four different types of stencils on three different GPU platforms shows that our hybrid method achieves speedups up to 2.93X over methods that use circular queues implemented with shared-memory only.

关键词： stencil computation circular queue GPU occupancy register

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Promoter recognition with machine learning algorithms keREM, RULSE-3 and ANN

Promoter recognition with machine learning algorithms keREM,...

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International Symposium on INnovations in Intelligent SysTems and Applications, INISTA 2012

作者： Karli, Günay Nayir, Ahmet Faculty of Engineering and Information Technology International Burch Universiy Sarajevo Bosnia and Herzegovina Department of Computer Programming Fatih University Istanbul Turkey

ISBN: (纸本)9781467314466

Data mining has become an important and active area of research because of theoretical challenges and practical applications associated with the problem of discovering interesting and previously unknown knowledge from very large real world database. These databases contain potential gold mine of valuable information, but it is beyond human ability to analyze massive amount of data and elicit meaningful patterns by using conventional techniques. In this study, DNA sequence was analyzed to locate promoter which is a regulatory region of DNA located upstream of a gene, providing a control point for regulated gene transcription. In this study, some supervised learning algorithms such as artificial neural network (ANN), RULES-3 and newly developed keREM rule induction algorithm were used to analyse to DNA sequence. In the experiments different option of keREM, RULES-3 and ANN were used, and according to the empirical comparisons, the algorithms appeared to be comparable to well-known algorithms in terms of the accuracy of the extracted rule in classifying unseen data. © 2012 IEEE.

关键词： Supervised learning

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