In the conditions of industrial production many processes of polymerisation are nonstationary. By processes optimization with the regard for such features as basic data it is necessary to use adaptive algorithms of id...
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In the conditions of industrial production many processes of polymerisation are nonstationary. By processes optimization with the regard for such features as basic data it is necessary to use adaptive algorithms of identification, allowing mathematical model of process continuously to be adapted for changing conditions of operation. Use of such algorithms for process optimization demands periodic recalculation of optimum technological modes of process. Polymer reaction engineering is a discipline that deals with various problems concerning the fundamental nature of chemical and physical phenomena in polymerization processes. Mathematical modeling is a powerful tool for the development of process understanding and advanced reactor technology in the polymer industry.
Fuzzy competition graph as the generalization of competition graph is introduced here. A generalization of fuzzy competition graph known as fuzzy k-competition graph is also defined. These graphs are related to fuzzy ...
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Fuzzy competition graph as the generalization of competition graph is introduced here. A generalization of fuzzy competition graph known as fuzzy k-competition graph is also defined. These graphs are related to fuzzy digraphs. Fuzzy neighbourhood graphs, which are related to fuzzy graphs are defined here. Some relations between fuzzy competition graphs and fuzzy neighbourhood graphs have been established. Also several results to find strong edges of the stated graphs are obtained.
The multilevel inverters (MLIs) are classified into three topologies such as Diode Clamped, Flying Capacitor and Cascade Multilevel Inverter (CMLI). CMLI topologies include two kind of structure that is named symmetri...
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Maintenance starts with reliable diagnostics. programming Logic Controllers (PLCs) are often equipped with a high degree of diagnostic procedures in order to ensure that the processing unit is functioning correctly. I...
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ISBN:
(纸本)9781629935881
Maintenance starts with reliable diagnostics. programming Logic Controllers (PLCs) are often equipped with a high degree of diagnostic procedures in order to ensure that the processing unit is functioning correctly. It is vital to verify that the system with its programme is still within a 'healthy' state, otherwise a safety function is called and the system is brought into a safe state, or if possible, defect and malfunctioning components are exchanged during operation and the process can continue without shutting down the system. However, when it comes to smaller devices such as intelligent sensors, embedded controller devices with the functionality of an e.g. PID (Proportional-Integral-Derivative), predictive controller, filter or analytical algorithm, which is embedded into a FPGA or micro-controller then diagnostics and verification methods are often not considered in the way they should be. For example, if an intelligent sensor system is not able to diagnose that the sensor-head is malfunctioning, but the sensor-head still provides some data, then the smart algorithm bases its calculation on wrong data, which can cause a dangerous situation. This paper investigates and shows recent results to combine diagnostic methods for small scale devices. Several safety-related structures are considered with a high degree of diagnostic coverage. The paper presents relevant procedures and structures to increase the reliability of small devices without utilising a full scale microcontroller system.
GPGPUs are increasingly being used to as performance accelerators for HPC （High Performance Computing） applications in CPU/GPU heterogeneous computing systems, including TianHe-1A, the world＇s fastest supercomputer...
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GPGPUs are increasingly being used to as performance accelerators for HPC （High Performance Computing） applications in CPU/GPU heterogeneous computing systems, including TianHe-1A, the world＇s fastest supercomputer in the TOP500 list, built at NUDT （National University of Defense technology） last year. However, despite their performance advantages, GPGPUs do not provide built-in fault-tolerant mechanisms to offer reliability guarantees required by many HPC applications. By analyzing the SIMT （single-instruction, multiple-thread） characteristics of programs running on GPGPUs, we have developed PartialRC, a new checkpoint-based compiler-directed partial recomputing method, for achieving efficient fault recovery by leveraging the phenomenal computing power of GPGPUs. In this paper, we introduce our PartialRC method that recovers from errors detected in a code region by partially re-computing the region, describe a checkpoint-based faulttolerance framework developed on PartialRC, and discuss an implementation on the CUDA platform. Validation using a range of representative CUDA programs on NVIDIA GPGPUs against FullRC （a traditional full-recomputing Checkpoint-Rollback-Restart fault recovery method for CPUs） shows that PartialRC reduces significantly the fault recovery overheads incurred by FullRC, by 73.5% when errors occur earlier during execution and 74.6% when errors occur later on average. In addition, PartialRC also reduces error detection overheads incurred by FullRC during fault recovery while incurring negligible performance overheads when no fault happens.
Networking technology, undoubtedly, plays a vital role in modern warfare especially in Network Centric Operations (NCOs) and Global Information Grid (GIG) concept. However, the current popular network infrastructure, ...
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The goal of Partitioned Global Address Space (PGAS) languages is to improve programmer productivity in large scale parallel machines. However, PGAS programs may have many fine-grained shared accesses that lead to perf...
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The multilevel inverters (MLIs) are classified into three topologies such as Diode Clamped, Flying Capacitor and Cascade Multilevel Inverter (CMLI). CMLI topologies include two kind of structure that is named symmetri...
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ISBN:
(纸本)9781467363914
The multilevel inverters (MLIs) are classified into three topologies such as Diode Clamped, Flying Capacitor and Cascade Multilevel Inverter (CMLI). CMLI topologies include two kind of structure that is named symmetric and asymmetric topologies. Asymmetric Cascade MLI (ACMLI) topologies consist of unequal DC sources. Many modulation techniques have been used in ACMLI topology such as Multi-Carrier PWM (MC-PWM), Space Vector PWM and Selective Harmonic PWM. The MC-PWM technique is achieved by four different types. In this study, MC-PWM techniques which are named Phase Disposition PWM, Phase Opposition Disposition PWM, Alternate Phase Opposition Disposition PWM and Phase Shifted PWM have been compared. It is uncovered that Phase Opposition Disposition PWM technique is more convenient in terms of Total Harmonic Distortion of output voltage and current signals and in terms of the quality of power factor in ACMLI which is performed in this study.
In this paper, we present a hybrid circular queue method that can significantly boost the performance of stencil computations on GPU by carefully balancing usage of registers and shared-memory. Unlike earlier methods ...
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In this paper, we present a hybrid circular queue method that can significantly boost the performance of stencil computations on GPU by carefully balancing usage of registers and shared-memory. Unlike earlier methods that rely on circular queues predominantly implemented using indirectly addressable shared memory, our hybrid method exploits a new reuse pattern spanning across the multiple time steps in stencil computations so that circular queues can be implemented by both shared memory and registers effectively in a balanced manner. We describe a framework that automatically finds the best placement of data in registers and shared memory in order to maximize the performance of stencil computations. Validation using four different types of stencils on three different GPU platforms shows that our hybrid method achieves speedups up to 2.93X over methods that use circular queues implemented with shared-memory only.
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