Categorizes the coherence traffic in update-based protocols and shows that, for most applications, more than 90% of all updates generated by such a protocol are unnecessary. We identify application characteristics tha...
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Categorizes the coherence traffic in update-based protocols and shows that, for most applications, more than 90% of all updates generated by such a protocol are unnecessary. We identify application characteristics that generate useless update traffic, and compare the isolated and combined effects of several software and hardware techniques for eliminating useless updates. These techniques include dynamic and static hybrid protocols, a data re-mapping strategy, and coalescing write buffers. Our simulations show that these techniques are effective for different types of useless updates. Overall, software caching (where dynamic data re-mapping is performed under programmer or compiler control) has the potential to significantly increase the percentage of useful traffic in applications. When software caching is not applicable, either the static or the dynamic protocol generates the least useless traffic. Although coalescing write buffers provide great reductions in the total number of messages transferred, these buffers do not necessarily increase the percentage of useful traffic.
With submicron technologies, gate delays are dominated by gate load delays rather than intrinsic gate delays. While the common approach for computing gate load delay (or total gate delay) is through delay tables (or k...
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With submicron technologies, gate delays are dominated by gate load delays rather than intrinsic gate delays. While the common approach for computing gate load delay (or total gate delay) is through delay tables (or k-factor equations), there are important methodology problems associated with the delay table approach. In this paper, we propose a gate driver model with a Thevenin equivalent circuit consisting of a ramp voltage source whose slew time is obtained from the gate slew tables, and a driver resistance in series with the gate load. We then develop analytical gate delay formulas using this Thevenin driver model and modeling the load with various gate load models under both rising and falling ramp input.
In this paper, we analyze coupled transmission lines and obtain a relationship between the moments of the coupled transfer functions. We then derive expressions for the first and second moments of the coupled transfer...
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In this paper, we analyze coupled transmission lines and obtain a relationship between the moments of the coupled transfer functions. We then derive expressions for the first and second moments of the coupled transfer function which can be used to compute the response and threshold delays under various input excitations. We can compute the interconnect delay under parasitic coupling effects by using the previously derived analytic delay formulas for step and ramp inputs. We also present the analysis to compute the general k/sup th/ moment for the coupled interconnect lines.
A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented in this paper. This method is based on structural decomposition of the circuit, ...
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A general method for determining whether a certain design is initializable, and for generating its initialization sequence, is presented in this paper. This method is based on structural decomposition of the circuit, and can handle both logical (using X-value simulation) and functional initializability. The routines developed are then used for ATPG of sequential circuits.
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However, for typical RLC interconnections with ramp input, ...
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Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However, for typical RLC interconnections with ramp input, Elmore delay can deviate by up to 100% or more from SPICE-computed delay since it is independent of rise time of the input ramp signal. We develop new analytical delay models based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. Delay estimates using our first moment based analytical models are within 4% of SPICE-computed delay, and models based on both first and second moments are within 2.3% of SPICE, across a wide range of interconnect parameter values. Evaluation of our analytical models is several orders of magnitude faster than simulation using SPICE. We also describe extensions of our approach for estimation of source-sink delays in arbitrary interconnect trees.
We present a fast resampling scheme using vector quantization. Our method differs from prior work applying vector quantization to speeding up image and volume processing in two essential aspects. First, our method use...
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The paper describes an implementation of a tool for visualizing and interacting with huge information hierarchies, and some preliminary empirical evaluation of the tool's efficacy. Existing systems for visualizing...
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The paper describes an implementation of a tool for visualizing and interacting with huge information hierarchies, and some preliminary empirical evaluation of the tool's efficacy. Existing systems for visualizing huge hierarchies using cone trees "break down" once the hierarchy to be displayed exceeds roughly 1000 nodes, due to increasing visual clutter. The paper describes a system called fsviz which visualizes arbitrarily large hierarchies while retaining user control. This is accomplished by augmenting cone trees with several graphical and interaction techniques: usage-based filtering, animated zooming, hand-coupled rotation, fish-eye zooming, coalescing of distant nodes, texturing, effective use of colour for depth cueing, and the applications of dynamic queries. The fsviz system also improves upon earlier cone tree visualization systems through a more elaborate node layout algorithm. This algorithm enhances the usefulness of cone tree visualization for large hierarchies by all but eliminating clutter.
We study a high order finite difference scheme to solve the time accurate flow field of a jet using the compressible Navier-Stokes equations. As part of OUT ongoing efforts, we have implemented our numerical model on ...
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