We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop w...
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We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach makes it suitable for the analysis loop within performance-driven iterative layout optimization. We present an iterationless approach for computing the effective capacitance of an interconnect load at a gate output when the slew time is non-zero (i.e., a ramp). We then extend this effective capacitance algorithm to complex gates, i.e., channel-connected components. Preliminary experimental results using the new effective capacitance approach show that the resulting delay estimates are quite accurate-within 15% of HSPICE-computed delays on data taken from a recent microprocessor design in 0.25 /spl mu/m CMOS technology. The improved driver model reduces the cell delay calculation errors to below 10%; this indicates that accurate modeling of effective capacitance is no longer the dominant source of errors in cell delay calculation.
We describe a simple system for producing synthetic 3D scenes integrated with real images captured with a camera, by using the graphic library, Open Inventor. All parts of the system are described: real image capture,...
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We describe a simple system for producing synthetic 3D scenes integrated with real images captured with a camera, by using the graphic library, Open Inventor. All parts of the system are described: real image capture, parameters measuring from the real scene, synthetic scene formation and coherent integration between the synthetic scene and the captured sequence. Finally we present some results of the proposed system.
The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. In this paper we present a closed-form crosstalk noise model with accuracy comparable to that of SPICE for an arbitra...
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The performance of high-speed VLSI circuits is increasingly limited by interconnect coupling noise. In this paper we present a closed-form crosstalk noise model with accuracy comparable to that of SPICE for an arbitrary ramp input. We also develop a simplified delay model for estimating delays on coupled RC lines considering input slew times for both agressor and victim lines. We then apply our model along with SPICE simulation to perform various studies of delay uncertainty in coupled interconnects. With respect to the effects of changing aggressor slew time on victim delay (i.e., delay variation), we observe that the victim delay is worst when the aggressor is switching very fast (e.g., step input). For local interconnects the delay variation (change in victim delay with varying input slew) can be as high as 70%. On the other hand, delay variation is around 10% for global interconnects. We also observe that the difference between minimum and maximum delay (i.e., delay uncertainty) decreases significantly as slew times are increased. Delay uncertainty on the victim wire is high for global wires as compared to local wires, a consequence of differing ratios of coupling to parallel-plate capacitance, and wire to load capacitance. We believe that our noise and delay analytical models form an effective basis for methodologies that lead to less over-design and guard-banding in high-performance system designs.
We describe a robust, exact, and efficient implementation of an algorithm that computes the width of a three-dimensional point set. The algorithm is based on efficient solutions to problems that are at the heart of co...
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Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized, cache-friendly codes. Where cycles ...
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