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The future of advanced driving assistance system development in China

The future of advanced driving assistance system development...

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IEEE International Conference on Vehicular Electronics and Safety (ICVES)

作者： Lian Duan Fang Chen Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden Interaction Design Department of Apply IT Chalmers University of Technology Gothenburg Sweden

Nowadays, with the rapid development of vehicle industry in China, an increasing number of companies realized the importance of culture adaption, when implementing ADAS (Advanced Driving Assistance System) to the vehicles in China. However, some designing issues of these systems need to be solved, taking consideration of driver's behavior and traffic situation in China. There is a lack of studies on Chinese drivers and related to HMI design of ADAS systems in the literature. There are limited reports on Chinese traffic and drivers studies, but still lack of the necessary depth. Some interaction design methodologies, including personas, focus group study, questionnaire and so on, were used in these reports. However, these studies are neither intensive nor comprehensive. Although (part of) the issues are brought up and analyzed, only general solutions are mentioned for the designing of the systems. Present paper, through literature review, indicated different areas that need to be focused on that are related to culture issues and the possible methodologies that can be applied.

关键词： Vehicles Roads Accidents Safety Cultural differences Monitoring Europe

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Communication service for hardware tasks executed on dynamic and partial reconfigurable resources

Communication service for hardware tasks executed on dynamic...

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IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

作者： Surya Narayanan Ludovic Devaux Daniel Chillet Sebastien Pillement Ioannis Sourdis Computer Engineering Delft University of Technology Delft Netherlands Cairn Laboratory INRIA France Computer Science and Engineering Department Chalmers University of Technology Sweden

The recent developments in the partial and dynamic Reconfigurable Computing (RC) domain demand better ways to manage the simultaneous task execution. In this context, Operating System (OS) services like scheduling, placement, inter-task communication have been developed to make this type of platform more flexible. In order to provide efficient communication scheme between these hardware tasks, a high performance communication infrastructure must be developed and efficient communication services must be proposed. The contribution presented in this paper mainly focuses on the hardware communication service and the communication schemes supported by this new OS service. Performance and implementation cost of our hardware communication service are evaluated and comparisons with the state of the art are given. Compared to related work OS4RS, our proposal is 60× faster to establish communication between hardware tasks.

关键词： Hardware Data communication Nickel System-on-a-chip Proposals Kernel

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Reconfigurable Instruction Decoding for a Wide-Control-Word Processor

Reconfigurable Instruction Decoding for a Wide-Control-Word ...

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IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Alen Bardizbanyan Magnus Sjalander Per Larsson-Edefors VLSI Research Group Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

Fine-grained control through the use of a wide control word can lead to high instruction-level parallelism, but unless compressed the words require a large memory footprint. A reconfigurable fixed-length decoding scheme can be created by taking advantage of the fact that an application only uses a subset of the data path for its execution. We present the first complete implementation of the Flex Core processor, integrating a wide control-word data path with a run-time reconfigurable instruction decompress or. Our evaluation, using three different EEMBC benchmarks, shows that it is possible to reach up to 35% speedup compared to a five-stage pipelined MIPS processor, assuming the same data path units. In addition, our VLSI implementations show that this FlexCore processor offers up to 24% higher energy efficiency than the MIPS reference processor.

关键词： Table lookup Clocks Benchmark testing Timing Registers Process control

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Application-Specific Energy Optimization of General-Purpose Datapath Interconnect

Application-Specific Energy Optimization of General-Purpose ...

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IEEE computer Society Annual Symposium on VLSI

作者： Babak Hidaji Salar Alipour Kasyab P. Subramaniyan Per Larsson-Edefors VLSI Research Group Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

A general-purpose data path is designed for efficient execution of diverse applications. An embedded processor, typically working with a limited application domain, does not necessarily utilize the fixed, general-purpose data path interconnect efficiently. If we consider the interconnect to be a flexible resource, the data path can be fine tuned to an application domain. The addition of an interconnect link between two data path units has the potential to reduce execution time, while the removal of an unused link can save area and power dissipation. Finding the most energy-efficient data path interconnect configuration for a software application domain is a time-consuming process, since it involves rescheduling of the targeted application(s) on different data path implementations. We present an automated optimization engine that is based on a genetic algorithm. This engine aids the designer in finding the most energy-efficient interconnect configuration of a simple processor data path. We show that an optimized data path interconnect can offer an energy saving of 38% with respect to a general-purpose data path reference, if the interconnect links are matched to the need of one application.

关键词： Biological cells Energy dissipation Optimization Engines Integrated circuit interconnections Correlation Benchmark testing

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FlexDEF: Development framework for processor architecture implementation and evaluation

FlexDEF: Development framework for processor architecture im...

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Ph.D. Research in Microelectronics and Electronics (PRIME)

作者： Kasyab P. Subramaniyan Erik Ryman Magnus Själander Tung Thanh Hoang Mafijul Md Islam Per Larsson-Edefors VLSI Research Group Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

Designing a processor is a complex task that uses multiple and varied tools. The complete development cycle spans software as well as hardware design and verification. More often than not, in spite of the close dependencies between hardware and software, there is no common platform for quick and accurate testing of these dependencies. Though such systems are often employed in industry, it is not common for end-to-end frameworks to be deployed in educational and research settings. We present the FlexCore Design Exploration Framework (FlexDEF), an end-to-end tool-chain used to develop the FlexCore processor and its accompanying cache system. The tool-chain is a hierarchically linked system that spans the various development phases involved in design and verification. The processor system is intended to be a model, for use in research-oriented projects where both the software and hardware are in a constant state of flux. We discuss the complete framework and the advantages in each context. Finally, we summarize the developments and discuss the future of the FlexDEF tool-chain.

关键词： Field programmable gate arrays Application specific integrated circuits Software Space exploration Hardware Table lookup

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Power gating multiplier of embedded processor datapath

Power gating multiplier of embedded processor datapath

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Ph.D. Research in Microelectronics and Electronics (PRIME)

作者： Tung Thanh Hoang Vineeth Saseendran Donatas Siaudinis Per Larsson-Edefors VLSI Research Group Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in embedded processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant idle times during the execution of the applications. We introduce power gating of individual datapath units for the embedded architecture of FlexCore, to evaluate if leakage reductions in temporarily idle units can reduce the overall power dissipation of compute-intensive applications. Post-layout multi-corner simulations for a 65-nm FlexCore datapath implementation demonstrate that power gating of the multiplier unit yields overall datapath energy savings, up to 14%, for two EEMBC benchmarks.

关键词： Switches Benchmark testing computer architecture Software Hardware Registers

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Executable and Translatable UML -- How Difficult Can it Be?

Executable and Translatable UML -- How Difficult Can it Be?

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Asia-Pacific Conference on Software engineering

作者： Hakan Burden Rogardt Heldal Toni Siljamaki Computer Science and Engineering Chalmers University of Technology University of Gothenburg Gothenburg Sweden Ericsson AB Stockholm Sweden

Executable and Translatable UML enables Model-Driven Architecture by specifying Platform-Independent Models that can be automatically transformed into Platform-Specific Models through model compilation. Previous research shows that the transformations result in both efficient code and consistency between the models. However, there are neither results for the effort of introducing the technology in a new context nor on the level of expertise needed for designing the Platform-Independent Models. We wanted to know if teams of novice software developers could design Executable and Translatable UML models without prior experiences of software modelling. As part of a new university course we conducted an exploratory case study with two data collections over two years. Bachelor students were given the task to design a hotel reservation system and the necessary test cases for verifying the functionality and structure of the models within 300 hours, using Executable and Translatable UML. In total, 43 out of 50 teams succeeded in delivering verified and consistent models within the time frame. During the second data collection the students were given limited tool training. This gave a raise in the quality of the models. Due to the executable feature of the models the students were given constant feedback on their design until the models behaved as expected, with the required level of detail and structure. Our results show that using Executable and Translatable UML does not require more expertise than a bachelor program in computer science. All in all, Executable and Translatable UML could play an important role in future software development.

关键词： Unified modeling language Object oriented modeling Computational modeling Java Software Programming Educational institutions

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Toward dependability benchmarking of partitioning operating systems

Toward dependability benchmarking of partitioning operating ...

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International Conference on Dependable Systems and Networks (DSN)

作者： Raul Barbosa Johan Karlsson Qiu Yu Xiaozhen Mao Department of Informatics Engineering University of Coimbra Coimbra Portugal Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

This paper describes a dependability benchmark intended to evaluate partitioning operating systems. The benchmark includes both hardware and software faultloads and measures the spatial as well as the temporal isolation among tasks, provided by a given real-time operating system. To validate the benchmark, a prototype implementation is carried out and three targets are benchmarked according to the specified process. The results substantiate that the proposed benchmark is able to compare and rank the targets in an objective way, and that it provides the ability to identify aspects of the target systems that need improvement.

关键词： Benchmark testing Operating systems Hardware Registers Real time systems Measurement

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CompSize: Automated Size Estimation of Embedded Software Components

CompSize: Automated Size Estimation of Embedded Software Com...

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Joint Conference of the Int'l Workshop on and International Conference on Software Process and Product Measurement Software Measurement

作者： Kenneth Lind Rogardt Heldal Tigran Harutyunyan Tony Heimdahl Electrical Systems Engineering Saab Automobile AB Trollhattan Sweden Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden University of Gothenburg Gothenburg Sweden Chalmers University of Technology Gothenburg Sweden

Accurate estimation of Software Code Size is important for developing cost-efficient embedded systems. The Code Size affects the amount of system resources needed, like ROM and RAM memory, and processing capacity. In our previous work, we have estimated the Code Size based on CFP (COSMIC Function Points) within 15% accuracy, with the purpose of deciding how much ROM memory to fit into products with high cost pressure. Central in that work is the mapping between CFP and the information available early in the development process. We have previously defined a UML Profile capturing the information needed for CFP measurement and estimation of Code Size. The key idea was to extend UML components to contain all the necessary information. In this paper, we show how we developed a tool for automated estimation of Code Size based on our UML Profile. The tool is designed to permit Code Size estimation based on other UML diagrams than components. A case study evaluates the UML Profile and the tool in a realistic case.

关键词： Unified modeling language Software Estimation Size measurement Random access memory Software measurement Electronic mail

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3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry

3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic a...

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Custom Integrated Circuits Conference (CICC)

作者： E. Ryman A. Emrich S. Andersson J. Riesbeck L. Svensson P. Larsson-Edefors Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden Omnisys Instruments AB Vastra Frolunda Sweden

A high-speed low-power cross-correlator ASIC has been implemented in a 65-nm CMOS process for the purpose of synthetic aperture radiometry from geostationary orbiting earth observation satellites. The chip performs cross-correlation on all individual signal pairs from 64 digital 1-bit inputs, which amounts to 2016 individual cross-correlation products. The experimental evaluation, using a specially developed PCB, demonstrates that the 3-mm 2 chip has a top performance of 3.6 GHz at a 1.2 V supply, at which it dissipates 790 mW.

关键词： Correlators Synchronization Clocks Apertures Delay Semiconductor device measurement Correlation

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