A common problem in optical motion capture is the so-called missing marker problem. The occlusion of markers can lead to significant loss of tracking accuracy unless continuous data flow is guaranteed by computational...
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We investigate the influence of a realistic supply voltage network on the timing margins for a commercially-available 32-bit processor chip. Detailed models of the supply network and switching activity produce a spati...
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Conventional IR drop analysis suggests that on-chip inductive effects can be neglected when estimating supply voltage drops. We present a supply voltage drop analysis for a commercial 32-bit application processor. Our...
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Yearly Almost 80,000 people are killed in traffic accidents in China due to the rapid growth of the number of *** safety has become one of the most important social problems that need to be *** data findings show that...
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Yearly Almost 80,000 people are killed in traffic accidents in China due to the rapid growth of the number of *** safety has become one of the most important social problems that need to be *** data findings show that driver behaviors are a part of the main contributing factor related to traffic *** is a need to increase safety and cars are being equipped with new active safety technology known as Advanced Driver Assistant Systems(ADAS) that helps by warning drivers before accidents occur.A simulator study with 16 participants was carried out using a driving simulator and an integrated visual interface prototype developed by chalmersuniversity of technology in Sweden. The interface presents information visually to the driver before any critical situation with help from three Advanced Driver Assistance Systems,Forward Collision Warning(FCW),Curve Speed Warning(CSW) and Lane Departure Warning(LDW).The prototype also provides critical sound warnings for FCW(if the driver is too close to the car in front),CSW(the driver has too high speed entering a curve) and LDW (when a lane departure occurs and the turn-lights are not used).Questionnaires and open-ended interviews were held to subjectively measure the participants' attitude toward the sound warnings and visual *** results showed that most participants thought the sound warning could facilitate their driving while most users' attitude towards the visual display warning were comparatively neutral. The majority of participants accepted the sound warnings and believed that they could help them perceive the potential danger in real driving *** results also showed that the sound warning system design needed to be improved as well,e.g.,many participants thought the sound warning occurred too frequently,especially for experienced *** is a need to conduct further studies to better understand how ADAS technology can be designed to suite Chines
The CHAMP (chalmers Architecture and Methodology for Flexible Production) system is a general control system for manufacturing that can be configured for arbitrary production. The same system can be used recursive at ...
The CHAMP (chalmers Architecture and Methodology for Flexible Production) system is a general control system for manufacturing that can be configured for arbitrary production. The same system can be used recursive at different levels of the production. The system consists of producers that can perform operations on products and movers that can move products between producers. Each product is described by a number of operations that are mapped to global operations in the database. Thus a flexible production can be designed only by defining the product recipes and the factory layout.
As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limited set of datapath units. By utilizing a flexible datapath interconnect and a wide control word, a FlexCore processor ...
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As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limited set of datapath units. By utilizing a flexible datapath interconnect and a wide control word, a FlexCore processor is explicitly designed to support integration of special units that, on demand, can accelerate certain data-intensive applications. In this paper, we propose the integration of a novel Double Throughput Multiply-Accumulate (DTMAC) unit, whose different operating modes allow for on-thefly optimization of computational precision. For the two EEMBC benchmarks considered, the FlexCore processor performance is significantly enhanced when one DTMAC accelerator is included, translating into reduced execution time and energy dissipation. In comparison to the 32-bit GPP reference, the accelerated 32-bit FlexCore processor shows a 4.37times improvement in execution time and a 3.92times reduction in energy dissipation, for a benchmark with many consecutive 16-bit MAC operations.
Today power optimization is an important field of research due to the increasing need for less power consumption, dramatic decrease of circuit's MTBF on high temperature and cooling difficulties. It is investigate...
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Today power optimization is an important field of research due to the increasing need for less power consumption, dramatic decrease of circuit's MTBF on high temperature and cooling difficulties. It is investigated that only 30% improvement in battery performance will be obtained in five years. This paper is an overview on power estimation and optimization researches and the overall flow of presenting the information is based on the reference. We review the architectural template and the methods to provide model for power consumption of different types of components. Some common optimization techniques including clock-gating, exploiting the common case of the design and managing voltage are being reviewed.
Timeout mechanisms are a useful feature for web applications. However, these mechanisms need to be used with care because, if used as-is, they are vulnerable to timing attacks. This paper focuses on internal timing at...
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Timeout mechanisms are a useful feature for web applications. However, these mechanisms need to be used with care because, if used as-is, they are vulnerable to timing attacks. This paper focuses on internal timing attacks, a particularly dangerous class of timing attacks, where the attacker needs no access to a clock. In the context of client-side web application security, we present JavaScript-based exploits against the timeout mechanism of the DOM (document object model), supported by the modern browsers. Our experimental findings reveal rather liberal choices for the timeout semantics by different browsers and motivate the need for a general security solution. We propose a foundation for such a solution in the form of a runtime monitor. We illustrate for a simple language that, while being more permissive than a typical static analysis, the monitor enforces termination-insensitive noninterference.
Many mobile devices have reached the point where the users' (active) working set is smaller than the amount of storage available and that trend is likely to continue. Currently these resources are made available f...
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Many mobile devices have reached the point where the users' (active) working set is smaller than the amount of storage available and that trend is likely to continue. Currently these resources are made available for recording new data, but we think that we could make better use of this capacity. Hoarding previously not accessed data could give better data coverage in cases of disconnected operation, when wireless networks are not available or access to them is expensive. We gathered a trace from a university file system used by more than 5000 people over a period of 16 months. This trace is used to drive a simulation model of distributed file systems. This paper studies a novel hoarding scheme that uses the access profile of other users to predict what files a user would need in the future. This hoarding scheme is shown to avoid between 30% and 75% of remote file accesses to files that are accessed for the first time. Furthermore, hoarded but not used data can be expired, because we note experimentally that the population shifts focus each month.
High-performance arithmetic circuits are critical to overall design performance and are therefore designed using full-custom design techniques. However, this is a time-consuming and error-prone task. We present a nove...
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ISBN:
(纸本)9781424450909;9781424450916
High-performance arithmetic circuits are critical to overall design performance and are therefore designed using full-custom design techniques. However, this is a time-consuming and error-prone task. We present a novel layout exploration methodology to design arithmetic circuits using standard-cell techniques, that retains competitive performance while allowing an almost custom-design kind of control over the layout. It uses an unconventional approach with a Haskell-based front-end in the Wired system, designed to produce logically and topologically accurate circuit descriptions and at the same time be parameterizable. Further, another overall goal of the system was to keep implementation time as low as possible. We demonstrate this methodology on HPM multipliers that exhibit a high degree of layout regularity.
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