While an important factor in depth perception, the occlusion effect in 3D environments also has a detrimental impact on tasks involving discovery, access, and spatial relation of objects in a 3D visualization. A numbe...
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While an important factor in depth perception, the occlusion effect in 3D environments also has a detrimental impact on tasks involving discovery, access, and spatial relation of objects in a 3D visualization. A number of interactive techniques have been developed in recent years to directly or indirectly deal with this problem using a wide range of different approaches. In this paper, we build on previous work on mapping out the problem space of 3D occlusion by defining a taxonomy of the design space of occlusion management techniques in an effort to formalize a common terminology and theoretical framework for this class of interactions. We classify a total of 25 different techniques for occlusion management using our taxonomy and then go on to analyze the results, deriving a set of five orthogonal design patterns for effective reduction of 3D occlusion. We also discuss the "gaps" in the design space, areas of the taxonomy not yet populated with existing techniques, and use these to suggest future research directions into occlusion management.
With the growing acceptance of multi-core architectures by the industry, devising novel techniques to extract thread-level parallelism from sequential programs has become a fundamental need. The role of compiler along...
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With the growing acceptance of multi-core architectures by the industry, devising novel techniques to extract thread-level parallelism from sequential programs has become a fundamental need. The role of compiler along with programming model and architectural innovation is of utmost importance to fully realize the potential performance benefits of the multi-core architectures. This paper evaluates the capabilities and limitations of parallelizing compilers to extract parallelism automatically from the loops present in sequential programs. The applications from embedded benchmark suites EEMBC 1.1 and MiBench are analyzed using the Intel C++ 9.1 Compiler for Linux. The contributions of the paper are manifold: Firstly, the paper shows that on average 10% of the loops can be parallelized automatically by the Intel Compiler. Secondly, we have shown that the auto- parallelizable loops cover only about 12.5% of the total program execution-time. Thirdly, we have explored the reasons behind the inability of the compiler to auto-parallelize the majority of the loops. We have found that on average 37.5% and 8% of the loops can't be auto-parallelized because of statically unknown loop trip count and probable data dependence, respectively. Finally, this study identifies the set of loops which comprises the most of the execution time of the programs and shows that compiler, on average, can automatically parallelize about 22% of such loops.
Information security has a challenge to address: enabling information-flow controls with expressive information release (or declassification) policies. Existing approaches tend to address some aspects of information r...
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ISBN:
(纸本)0769528481;9780769528489
Information security has a challenge to address: enabling information-flow controls with expressive information release (or declassification) policies. Existing approaches tend to address some aspects of information release, exposing the other aspects for possible attacks. It is striking that these approaches fall into two mostly separate categories: revelation-based (as in information purchase, aggregate computation, moves in a game, etc.) and encryption-based declassification (as in sending encrypted secrets over an untrusted network, storing passwords, etc.). This paper introduces gradual release, a policy that unifies declassification, encryption, and key release policies. We model an attacker's knowledge by the sets of possible secret inputs as functions of publicly observable outputs. The essence of gradual release is that this knowledge must remain constant between releases. Gradual release turns out to be a powerful foundation for release policies, which we demonstrate by formally connecting revelation-based and encryption-based declassification. Furthermore, we show that gradual release can be provably enforced by security types and effects.
Instruction reuse (IR) and trivial computation (TC) elimination are two architectural techniques that aim at eliminating redundant code to better exploit instruction-level parallelism. While they have been extensively...
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Instruction reuse (IR) and trivial computation (TC) elimination are two architectural techniques that aim at eliminating redundant code to better exploit instruction-level parallelism. While they have been extensively studied in isolation, this paper is the first to compare their relative efficiency. This is done using applications from the embedded domain. This paper establishes the relationship between the two techniques by framing the arithmetic instructions detected by each of them. While TC can only eliminate instructions where one of the operands is zero or one, IR has potentially a wider scope as it can potentially eliminate any instruction given that it has been executed before with the same set of operand values. Despite the wider scope, we have found that IR and TC can eliminate about the same fraction of instructions even if an infinitely large instruction reuse buffer is assumed (IR and TC can eliminate 26% and 22% of the instructions, respectively). Another quite surprising finding is that the two techniques target quite different sets of instructions suggesting that they can provide almost additive gains if combined. In combination, they can eliminate 40% of the instructions they target. In terms of energy-efficiency, we finally find that if an instruction reuse buffer of 256 entries is used, it uses 1% more energy than a processor without IR and TC reduces the energy consumption by 5.6%.
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, incl...
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We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling, for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction. Using the proposed methodology, dynamic, leakage and total power of partitioned SRAM arrays can be estimated with a 97% accuracy in comparison to the power obtained by running full circuit-level simulations.
We investigate the effects of introducing a flexible interconnect into an exposed datapath. We define an exposed datapath as a traditional GPP datapath that has its normal control removed, leading to the exposure of a...
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ISBN:
(纸本)9780769528960
We investigate the effects of introducing a flexible interconnect into an exposed datapath. We define an exposed datapath as a traditional GPP datapath that has its normal control removed, leading to the exposure of a wide control word. For an FFT benchmark, the introduction of a flexible interconnects reduces the total execution time by 16%. Compared to a traditional GPP, the execution time for an exposed datapath using a flexible interconnect is 32% shorter whereas the energy dissipation is 29% lower. Our investigation is based on a cycle-accurate architectural simulator and figures on delay, power, and area are obtained from placed-and-routed layouts in a commercial 0.13-mum technology. The results from our case studies indicate that by utilizing a flexible interconnect, significant performance gains can be achieved for generic applications.
This paper describes a study where drivers' responses to an invehicle information system were tested in high and low density traffic. There were 17 participants in a study that was run using a driving simulator. D...
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This article describes the modeling of clinical examinations in oral medicine using OWL. Based on experiences from our previous work and knowledge model, requirements for an ontology for examinations in oral medicine ...
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This article describes the modeling of clinical examinations in oral medicine using OWL. Based on experiences from our previous work and knowledge model, requirements for an ontology for examinations in oral medicine are identified. OWL can be used to address most, but not all, of the requirements. We found a lack of guidance for several design choices and for development of OWL ontologies at different levels of sophistication. However, using OWL gives us the ability to come back and refine the knowledge model after initial deployment.
In this paper, we validate our previously proposed high- level power estimation models for a 65-nm BPTM process, using a physically partitioned 2-kB 6T-SRAM array. Also, we describe a new probing methodology that allo...
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In this paper, we validate our previously proposed high- level power estimation models for a 65-nm BPTM process, using a physically partitioned 2-kB 6T-SRAM array. Also, we describe a new probing methodology that allows us to accurately capture not only subthreshold leakage, but also all other significant leakage mechanisms. By combining the probing methodology and the power models, we can estimate dynamic, leakage and total power of the partitioned 2-kB memory array with a 97% accuracy of that of full circuit-level simulations of the entire array. We also discuss the effect of partitioning on SRAM array power with respect to process technology scaling: Partitioning has the effect that leakage power constitutes an increasing fraction of total memory power, emphasizing the need to accurately capture leakage power in SRAM power models.
In this paper, we present a large-scale interactive book browsing installation for children's libraries called StorySurfer. The StorySurfer prototype is developed within the Interactive Children's Library proj...
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ISBN:
(纸本)9781595937476
In this paper, we present a large-scale interactive book browsing installation for children's libraries called StorySurfer. The StorySurfer prototype is developed within the Interactive Children's Library project, which includes interests from within design, research, industry, and libraries. The objective of the project is to give room for and encourage the physical activities of children, while pursuing to connect these with the basic digital and analogue services of the library e.g. borrowing and handing in books, searching for information, and providing access to a rich variety of media. Copyright 2007 ACM.
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