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IEEE International Conference on Microelectronic Systems Education

作者： E. Axelsson M. Bjrk M. Sheeran Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

Since 1999, the formal methods group of the Department of Computing science at chalmers university of technology has given a course on hardware description and verification (http://***/Cs/Education/Courses/svh/). The course focuses on the use of hardware description languages in design, and on functional verification using simulation, assertion monitoring and formal methods. The course is part of an international masters programme in dependable computer systems, although currently the majority of the students are from the 3rd and 4th years of the chalmers undergraduate programmes in electronics or computer engineering. About 35 students pass the course each year. The emphasis in the course is on practical approaches to hardware description and verification, with students gaining hands-on experience of both commercial and academic tools. In addition, the important concepts and algorithms underlying formal verification are taught. The fact that the course manages to reflect both advanced industrial practice and state of the art research is, we feel, its major strength. The paper emphasises the benefits that the course has brought to our research group.

关键词： Hardware design languages computer science education Electronics engineering education Continuing education

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A low-power FIR filter using combined residue and radix-2 signed-digit representation

A low-power FIR filter using combined residue and radix-2 si...

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Euromicro Symposium on Digital System Design

作者： A. Lindahl L. Bengtsson Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

This paper presents a FIR filter combining residue (RNS) and radix-2 signed digit (SD) representation. RNS offers parallelization of the computations and SD carry-free additions. The moduli set {2/sup n/-1, 2/sup n/, 2/sup n/+1} is used reducing the complexity of the RNS arithmetic units. The evaluated filters have 8, 12 and 16 taps, binary word lengths between 16 and 64 bits, and have been synthesized using a UMC 0.13 /spl mu/m CMOS cell library with 8 metal layers. Power, delay, and area comparisons are made with equivalent 2's complement designs. The area-delay and area-delay-power products shows that reduction in both power and area at the same filter throughput can be expected.

关键词： Finite impulse response filter Adders Arithmetic Delay computer science Design engineering Digital systems Logic circuits

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Reactive spin-locks: a self-tuning approach

Reactive spin-locks: a self-tuning approach

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International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN)

作者： P.H. Ha M. Papatriantafilou P. Tsigas Department of Computer Science and Engineering Chalmers University of Technology Goteborg Sweden

Reactive spin-lock algorithms that can automatically adapt to contention variation on the lock have received great attention in the field of multiprocessor synchronization, since they can help applications achieve good performance in all possible contention conditions. However, in existing reactive spin-locks the reaction relies on (i) some fixed experimentally tuned thresholds, which may get frequently inappropriate in dynamic environments like multiprogramming/multiprocessor systems, or (ii) known probability distributions of inputs. This paper presents a new reactive spin-lock algorithm that is completely self-tuning, which means no experimentally tuned parameter nor probability distribution of inputs are needed. The new spin-lock is built on a competitive online algorithm. Our experiments, which use the Spark98 kernels and the SPLASH-2 applications as application benchmarks, on a multiprocessor machine SGI Origin2000 and on an Intel Xeon workstation show that the new self-tuning spin-lock helps applications with different characteristics achieve good performance in a wide range of contention levels.

关键词： Probability distribution Switches Multiprocessing systems Parallel processing Interference Telecommunication traffic Traffic control Testing Delay computer science

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Implementing kilo-instruction multiprocessors

Implementing kilo-instruction multiprocessors

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2nd IEEE International Conference on Pervasive Services (ICPS 2005)

作者： Vallejo, E Galluzzi, M Cristal, A Vallejo, F Beivide, R Smith, JE Valer, M Stenström, P Grupo de Arquitectura de Computadores Universidad de Cantabria Spain Departament d'Arquitectura de Computadors Universitat Politècnica de Catalunya Spain Dept. of Computer Science and Engineering Chalmers University of Technology Sweden Dept. of Electrical and Computer Engineering University of Wisconsin Madison United States

ISBN: (纸本)0780390326

Multiprocessors are coming into wide-spread use in many application areas, yet there are a number of challenges to achieving a good tradeoff between complexity and performance. For example, while implementing memory coherence and consistency is essential for correctness, efficient implementation of critical sections and synchronization points is desirable for performance. The multi-checkpointing mechanisms of Kilo Instruction Processors can be leveraged to achieve good complexity-effective multiprocessor designs. We describe how to implement a Kilo-Instruction Multiprocessor that transparently, i.e. without any software support, uses transaction-based memory updates. Our model not only simplifies memory coherence and consistency hardware, but at the same time, it provides the potential for implementing high performance speculative mechanisms for commonly occurring synchronization constructs.

关键词： Program processors

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Dynamic and fault-tolerant cluster management

Dynamic and fault-tolerant cluster management

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International Conference on Peer-to-Peer Computing

作者： A. Gidenstam B. Koldehofe M. Papatriantafilou P. Tsigas Department of Computer Science and Engineering Chalmers University of Technology South Korea School of Computer and Communication Science Swiss Federal Institute of Technology Switzerland

Recent decentralised event-based systems have focused on providing event delivery which scales with increasing number of processes. While the main focus of research has been on ensuring that processes maintain only a small amount of information on maintaining membership and routing, an important factor in achieving scalability for event-based peer-to-peer dissemination system is the number of events disseminated at the same time. This work presents a dynamic and fault tolerant cluster management method which can be used to coordinate concurrent access to resources in a peer-to-peer system. In the context of event-based dissemination systems the cluster management can be used to control the number of concurrently disseminated events. We present and analyse an algorithm implementing the proposed cluster management model in a fault-tolerant and decentralised way. The algorithm provides for each cluster a limited set of tickets. A process which has obtained a ticket may send events corresponding to the resources of the cluster. The algorithm guarantees that no two processes ever issue an event corresponding to the same ticket at the same time. The cluster management model on its own has interesting properties which can be useful for many peer-to-peer applications.

关键词： Fault tolerance Peer to peer computing Clustering algorithms Algorithm design and analysis Routing Scalability Fault tolerant systems Resource management Control systems Collaboration

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Implementing Kilo-Instruction Multiprocessors

Implementing Kilo-Instruction Multiprocessors

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IEEE/ACS International Conference on Pervasive Services (ICPS)

作者： E. Vallejo M. Galluzzi A. Cristal F. Vallejo R. Beivide P. Stenstrom J.E. Smith M. Valero Grupo de Arquitectura de Computadores Universidad de Cantubria Spain Grupo de Arquitectura de Computadores Universidad de Cantabria Departament d'Arquitectura de Computadors Universitat Politècnica de Catalunya Spain Departament d'Arquitectura de Computadors Universitat Politècnica de Catalunya Dept of Computer Science and Engineering Chalmers University of Technology Sweden Dept. of Electrical and Computer Engineering University of Wisconsin-Madison USA

Multiprocessors are coming into wide-spread use in many application areas, yet there are a number of challenges to achieving a good tradeoff between complexity and performance. For example, while implementing memory coherence and consistency is essential for correctness, efficient implementation of critical sections and synchronization points is desirable for performance. The multi-checkpointing mechanisms of Kilo-Instruction Processors can be leveraged to achieve good complexity-effective multiprocessor designs. We describe how to implement a Kilo-Instruction Multiprocessor that transparently, i.e. without any software support, uses transaction-based memory updates. Our model not only simplifies memory coherence and consistency hardware, but at the same time, it provides the potential for implementing high performance speculative mechanisms for commonly occurring synchronization constructs.

关键词： Coherence Memory management Hardware Delay Access protocols Yarn Proposals Time to market computer science Application software

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Volt-amper characteristics parameters research of the power semiconductor devices in the conditions of low conducting ability.

Volt-amper characteristics parameters research of the power ...

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International Conference on Actual Problems of Electronic Instrument engineering (APEIE)

作者： N.N. Bespalov N.V. Trofimov Dept. of Computer Science and Engineering Chalmers University of Technology Sweden Dept. of Computer Science University of York York UK

The models of static and dynamic volt-amper semiconductor devices in the conditions of low conducting ability with different values of operating temperature have been elaborated. The evaluation of the approximate erro... 详细信息

关键词： Power semiconductor devices Semiconductor devices Pulse width modulation Pulse width modulation converters Power generation Temperature Power measurement Semiconductor device measurement Power system modeling

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MCK: Model checking the logic of knowledge

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Lecture Notes in computer science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2004年 3114卷 479-483页

作者： Gammie, Peter Van Der Meyden, Ron Computing Science Chalmers Institute of Technology Sweden School of Computer Science and Engineering University of New South Wales National ICT Australia Sydney NSW Australia

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Protecting security policies in ubiquitous environments using one-way functions

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in computer science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2004年 2802卷 71-85页

作者： Kvarnström, Håkan Hedbom, Hans Jonsson, Erland Department of Computer Engineering Chalmers University of Technology SE-412 96 Göteborg Sweden Telia Research AB Vitsandsgatan 9 SE-123 86 Farsta Sweden Department of Computer Science Karlstad University SE-651 88 Karlstad Sweden

This paper addresses the problem of protecting security policies and other security-related information in security mechanisms, such as the detection policy of an Intrusion Detection System or the filtering policy of a firewall. Unauthorized disclosure of such information can reveal the fundamental principles and methods for the protection of the whole network, especially in ubiquitous environments where a large number of nodes store knowledge about the security policy of their domain. To avoid this risk we suggest a scheme for protecting stateless security policies using one-way functions. A stateless policy is one that only takes into consideration, the current event, and not the preceding chain of events, when decisions are made. The scheme has a simple and basic design but can still be used for practical implementations, as illustrated in two examples in real-life enviroments. Further research aims to extend the scheme to stateful policies. © Springer-Verlag 2004.

关键词： Intrusion detection

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Low order sampled data H/sub /spl infin// control using the delta operator and LMIs

Low order sampled data H/sub /spl infin// control using the ...

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IEEE Conference on Decision and Control

作者： B. Lennartson R. Middleton A.-K. Christiansson T. McKelvey Control and Automation Laboratory Department of Signals and Systems Chalmers University of Technology Goteborg Sweden Complex Dynamic Systems & Control School of Electrical Engineering & Computer Science University of Newcastle Callaghan NSW Australia University of Trollhättan/Uddevalla Trollhattan Sweden Department of Signals and Systems Chalmers University of Technology Goteborg Sweden

A procedure for H/sub /spl infin// optimization of low order controllers for discrete-time and sampled-data systems is presented in this paper. Generally, low order H/sub /spl infin// controllers may be achieved by solving bilinear matrix inequalities (BMIs). In this paper an iterative alternation between two LMIs gives a suboptimal solution. To avoid local minima in this search the initial controller is obtained by a frequency weighted controller reduction scheme, where the closed loop properties of a full order controller is taken into account. A minimal number of parameters in the state space realization of the controller also reduces the complexity and improves numerical robustness. The complete presentation is based on delta operator models, which shows a close relationship between the continuous- and discrete-time solutions. The sensitivity of the ordinary discrete-time shift operator LMI formulation to small sampling periods is also analyzed.

关键词： Control systems Linear matrix inequalities Sampling methods Automatic control Frequency Weight control Robust control Signal processing State-space methods Robustness

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