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A hybrid system for patent translation 16

A hybrid system for patent translation

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16th Annual Conference of the European Association for Machine Translation, EAMT 2012

作者： Enache, Ramona España-Bonet, Cristina Ranta, Aarne Màrquez, Lluís Dept. of Computer Science and Engineering Chalmers University of Technology University of Gothenburg Sweden TALP Research Center LSI Department Universitat Politècnica de Catalunya Spain

This work presents a HMT system for patent translation. The system exploits the high coverage of SMT and the high precision of an RBMT system based on GF to deal with specific issues of the language. The translator is specifically developed to translate patents and it is evaluated in the English-French language pair. Although the number of issues tackled by the grammar are not extremely numerous yet, both manual and automatic evaluations consistently show their preference for the hybrid system in front of the two individual translators. © 2012 European Association for Machine Translation.

关键词： Hybrid systems

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Impact of soft errors in a jet engine controller

Impact of soft errors in a jet engine controller

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31st International Conference on computer Safety, Reliability, and Security, SAFECOMP 2012

作者： Hannius, Olof Karlsson, Johan Volvo Aero Corporation S-46181 Trollhättan Sweden Department of Computer Science and Engineering Chalmers University of Technology S-412 96 Göteborg Sweden

ISBN: (纸本)9783642336775

We present an experimental study in which we investigate the impact of particle induced soft errors occurring in the microprocessor of an experimental FADEC system. The study focuses on the impact of single bit faults in the instruction set architecture (ISA) registers. For such faults, we investigate the effectiveness of the error detection mechanisms included in the FADEC system, and determine the consequences of errors that escape detection. To this end, we injected single bit faults in the ISA registers of a Freescale MC68340 microprocessor during execution of a prototype jet engine control program. Utilizing both random fault injection and partially exhaustive injections, we conducted six fault injection campaigns comprising in total more than 7000 injected faults. Twenty-three percent of the injected faults were effective, i.e., they affected the outputs of the control program. Of these, the system detected 91%. Of the 9 % that escaped detection, 7% caused a minor deviation in engine thrust that would be harmless to flight safety, while 2% caused severe or potentially catastrophic changes in engine thrust. © 2012 Springer-Verlag.

关键词： Controllers

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Gulliver: A Test-Bed for Developing, Demonstrating and Prototyping Vehicular Systems

Gulliver: A Test-Bed for Developing, Demonstrating and Proto...

引用

IEEE Conference on Vehicular technology (VTC)

作者： Mitra Pahlavan Marina Papatriantafilou Elad M. Schiller Computer Science and Engineering Chalmers University of Technology Goteborg Sweden

Vehicular system designers often use simulation tools in order to prove vehicular systems. The computational complexity of detailed simulations limits the scale of such testings. Therefore, it is often the case that the first full-scale demonstrations of new concepts for vehicular systems are done in proving grounds and testing tracks. We propose Gulliver as a platform for studying vehicular systems on a large scale open source test-bed of low cost miniature vehicles that use wireless communication and are equipped with onboard sensors. Our approach provides a simpler yet detailed investigation of vehicular systems. This paper presents the platform with its design and a set of applications that could be demonstrated by Gulliver. Gulliver allows the design of vehicular systems to focus on the cyber-physical aspects of the studied problems. We expect that Gulliver will allow affordability and flexibility for a wider range of researchers to directly contribute to the development of future vehicular systems, such as greener transportation initiatives and zero fatality objectives.

关键词： Vehicles Testing Prototypes Computational modeling Sensors Humans Educational institutions

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Securing Interactive Programs

Securing Interactive Programs

引用

computer Security Foundations Workshop

作者： Willard Rafnsson Daniel Hedin Andrei Sabelfeld Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

This paper studies the foundations of information-flow security for interactive programs. Previous research assumes that the environment is total, that is, it must always be ready to feed new inputs into programs. However, programs secure under this assumption can leak the presence of input. Such leaks can be magnified to whole-secret leaks in the concurrent setting. We propose a framework that generalizes previous research along two dimensions: first, the framework breaks away from the totality of the environment and, second, the framework features fine-grained security types for communication channels, where we distinguish between the security level of message presence and message content. We show that the generalized framework features appealing compositionality properties: parallel composition of secure program results in a secure thread pool. We also show that modeling environments as strategies leads to strong compositionality: various types of composition (with and without scoping) follow from our general compositionality result. Further, we propose a type system that supports enforcement of security via fine-grained security types.

关键词： Security Message systems Observers Feeds Computational modeling Labeling Nickel

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Industrial Applicability of Visual GUI Testing for System and Acceptance Test Automation

Industrial Applicability of Visual GUI Testing for System an...

引用

International Conference on Software Testing, Verification, and Validation, ICST

作者： Emil Borjesson Department of Computer Science and Engineering Chalmers University of Technology Goteborg Sweden

The software market is becoming more challenging as demands for faster time-to-market and higher software quality continue to grow. These challenges are embedded in all areas of Software engineering, including Verification and Validation where they are proposed as solvable with automated testing. However, most automated testing techniques focus on low system level testing and are not suitable for high level tests, i.e. System and Acceptance tests, leaving industrial needs for test automation unfulfilled. In this paper we present a research plan to evaluate a novel automated testing technique, called visual GUI testing, based on image recognition algorithms and scripts that interact through the system GUI to automate complex scenario based tests. The technique has been evaluated at the company Saab AB where industrial, safety critical, scenario based, test cases were automated showing the industrial applicability of the technique. However, many factors are still unknown regarding the techniques industrial applicability, i.e. script maintenance costs, usability and learn ability, etc. Our research aims to uncover these unknown factors with the final research goal to show that visual GUI testing is a viable and cost-effective technique that will fill the gap in industry for a cost-effective, simple, robust, high-level test automation technique.

关键词： Testing Graphical user interfaces Visualization Industries Automation Robustness Maintenance engineering

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Architecture-level fault-tolerance for biomedical implants

Architecture-level fault-tolerance for biomedical implants

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International Conference on Embedded computer Systems: Architectures, Modeling and Simulation (IC-SAMOS)

作者： Robert M. Seepers Christos Strydis Georgi N. Gaydadjiev Faculty of Electrical Engineering Mathematics and Computer Science Delft University of Technology Netherlands Department of Computer Science and Engineering Chalmers University of Technology Sweden

In this paper, we describe the design and implementation of a new fault-tolerant RISC-processor architecture suitable for a design framework targeting biomedical implants. The design targets both soft and hard faults and is original in efficiently combining as well as enhancing classic fault-tolerance techniques. The proposed architecture allows run-time tradeoffs between performance and fault tolerance by means of instruction-level configurability. The system design is synthesized for UMC 90nm CMOS standard-process and is evaluated in terms of fault coverage, area, average power consumption, total energy consumption and performance for various duplication policies and test-sequence schedules. It is shown that area and power overheads of approximately 25% and 32%, respectively, are required to implement our techniques on the baseline processor. The major overheads of the proposed architecture are performance (up to 107%) and energy consumption (up to 157%). It is observed that the average power consumption is often reduced when a higher degree of fault tolerance is targeted. It is shown that test sequences can effectively be scheduled during the available program stalls and that nearly all soft faults are tolerated by using instruction duplication. The main advantages of the proposed architecture are the high portability of the introduced architecture-level fault-tolerance techniques, the flexibility in trading processor overheads for required fault-tolerance degree as well as affordable area and power consumption overheads.

关键词： Fault tolerance Fault tolerant systems Circuit faults Registers Runtime Hardware computer architecture

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Scalability Study of Polymorphic Register Files

Scalability Study of Polymorphic Register Files

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Euromicro Symposium on Digital System Design

作者： Catalin Ciobanu Georgi Kuzmanov Georgi Gaydadjiev Department of Computer Science and Engineering Chalmers University of Technology Sweden Computer Engineering Laboratory EEMCS Delft University of Technology Netherlands

We study the scalability of multi-lane 2D Polymorphic Register Files (PRFs) in terms of clock cycle time, chip area and power consumption. We assume an implementation which stores data in a 2D array of linearly addressable memory banks, and consider one single-view and four suitable multi-view parallel access schemes which cover all basic access patterns commonly used in scientific and multimedia applications. The PRF design features 2 read and 1 write ports, targeting the TSMC 90nm ASIC technology. We consider three PRF sizes - 32KB, 128KB and 512KB and four multi-lane configurations - 8 / 16 / 32 and 64 lanes. Synthesis results suggest that the clock frequency varies between 500MHz for a 512KB PRF with 64 vector lanes and 970Mhz for a 32KB / 8-lanes case. Estimated power consumption ranges from less than 300mW (dynamic) and 10mW (leakage) for our 8-lane, 32KB PRF up to 8.7W (dynamic) and 276mW (leakage) for a 512KB with 64 lanes. We also show the correlation among the storage capacity, the number of lanes, and the chip overall area. Furthermore, we also investigated customized addressing functions. Our experimental results suggest up to 21% increase of the clock frequency, and up to 39% combinational hardware area reduction (nearly 10% of the total area) compared to our straightforward implementations. Concerning power, we reduce dynamic power with up to 31% and leakage with nearly 24%.

关键词： Registers Vectors Clocks Scalability computer architecture Hardware

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On implementability of Polymorphic Register Files

On implementability of Polymorphic Register Files

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International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

作者： Cătălin Ciobanu Georgi Kuzmanov Georgi Gaydadjiev Department of Computer Science and Engineering Chalmers University of Technology Sweden Computer Engineering Laboratory EEMCS Delft University of Technology Netherlands

This paper studies the implementability of performance efficient multi-lane Polymorphic Register Files (PRFs). Our PRF implementation uses a 2D array of p × q linearly addressable memory banks, with customized addressing functions to avoid address routing circuits. We target one single-view and a set of four non redundant multi-view parallel memory schemes that cover all widely used access patterns in scientific and multimedia applications: 1) p × q rectangle, p · q row, p · q main and secondary diagonals; 2) p × q rectangle, p · q column, p · q main and secondary diagonals; 3) p · q row, p · q column, aligned p × q rectangle; 4) p × q, q × p rectangles (transposition). Reconfigurable hardware was chosen for the implementation due to its potential in enhancing the PRF runtime adaptability. For a proof of concept, we prototyped a 2 read, 1 write ports PRF on a Virtex-7 XC7VX1140T-2 FPGA. We consider four sizes for the 16 lanes PRFs - 16 × 16, 32 × 32, 64 × 64 and 128 × 128 and three multi-lane configurations, 8, 16 and 32, for the 128 × 128 PRF. Synthesis results suggest clock frequencies between 111 MHz and 326 MHz while utilizing less than 10% of the available LUTs. By using customized addressing functions, the LUT usage is reduced by up to 29% and the clock frequency is up to 77% higher compared to a straight-forward implementation.

关键词： Registers Vectors Runtime computer architecture Field programmable gate arrays Program processors Shape

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Physarum-inspired self-biased walkers for distributed clustering

Physarum-inspired self-biased walkers for distributed cluste...

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16th International Conference on Principles of Distributed Systems, OPODIS 2012

作者： Sohier, Devan Georgiadis, Giorgos Clavière, Simon Papatriantafilou, Marina Bui, Alain Department of Computer Science and Engineering Chalmers University of Technology S-412 96 Göteborg Sweden Université de Versailles St.-Quentin-en-Yvelines 78035 Versailles France

ISBN: (纸本)9783642354755

We propose a distributed scheme to compute distance-based clusters. We first present a mechanism based on the flow of distributed tokens called walkers, circulating randomly between a source and a sink to compute a shortest path. Each time a walker takes an edge, it reinforces the probability that subsequent walkers take it. This mechanism is a discrete emulation of the slime mould (Physarum polycephalum) dynamics presented in [16]: each node observes the flow of walkers going through each adjacent edge and uses this flow to compute the probabilities with which it sends the walkers through each edge. Then, based on this mechanism, we show how several sources compute a shortest path DAG to a given sink. Finally, given some clusterheads acting like sinks, we show that this process converges to distance-based clusters (i.e. nodes join the clusterhead to which they are closest) with shortest-path DAGs. The algorithm is designed with a special focus on dynamic networks: the flow locally adapts to the appearance and disappearance of links and nodes, including clusterheads. © 2012 Springer-Verlag.

关键词： Graph theory

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Multilingual Online generation from Semantic Web ontologies

Multilingual Online generation from Semantic Web ontologies

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21st Annual Conference on World Wide Web, WWW'12

作者： Dannélls, Dana Damova, Mariana Enache, Ramona Chechev, Milen University of Gothenburg and GSLT Department of Swedish Language SE-405 30 Gothenburg Sweden Ontotext AD Tsarigradsko Shosse 47A Sofia 1784 Bulgaria University of Gothenburg Department of Computer Science and Engineering SE-412 96 Gothenburg Sweden Chalmers University of Technology Department of Computer Science and Engineering SE-412 96 Gothenburg Sweden

ISBN: (纸本)9781450312301

In this paper we report on our ongoing work in the EU project Multilingual Online Translation (MOLTO), supported by the European Union Seventh Framework Programme under grant agreement FP7-ICT-247914. More specifically, we present work workpackage 8 (WP8): Case Study: Cultural Heritage. The objective of the work is to build an ontologybased multilingual application for museum information on the Web. Our approach relies on the innovative idea of Reason-able View of the Web of linked data applied to the domain of cultural heritage. We have been developing a Web application that uses Semantic Web ontologies for generating coherent multilingual natural language descriptions about museum objects. We have been experimenting with museum data to test our approach and find that it performs well for the examined languages. Copyright is held by the International World Wide Web Conference Committee (IW3C2).

关键词： Ontology

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