Cyber theft is a serious threat to Internet security. It is one of the major security concerns by both network service providers and Internet users. Though sensitive information can be encrypted when stored in non-vol...
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Cyber theft is a serious threat to Internet security. It is one of the major security concerns by both network service providers and Internet users. Though sensitive information can be encrypted when stored in non-volatile memory such as hard disks, for many e-commerce and network applications, sensitive information is often stored as plaintext in main memory. Documented and reported exploits facilitate an adversary stealing sensitive information from an application's memory. These exploits include illegitimate memory scan, information theft oriented buffer overflow, invalid pointer manipulation, integer overflow, password stealing Trojans and so forth. Today's computing system and its hardware cannot address these exploits effectively in a coherent way. This paper presents a unified and lightweight solution, called InfoShield that can strengthen application protection against theft of sensitive information such as passwords, encryption keys, and other private data with a minimal performance impact. Unlike prior whole memory encryption and information flow based efforts, InfoShield protects the usage of information. InfoShield ensures that sensitive data are used only as defined by application semantics, preventing misuse of information. Comparing with prior art, InfoShield handles a broader range of information theft scenarios in a unified framework with less overhead. Evaluation using popular network client-server applications shows that InfoShield is sound for practical use and incurs little performance loss because InfoShield only protects absolute, critical sensitive information. Based on the profiling results, only 0.3% of memory accesses and 0.2% of executed codes are affected by InfoShield.
Accuracy of information transmission when a signal must be transmitted through a communication channel is of essential importance in design of communication systems. When system resources are limited, such as transmis...
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Accuracy of information transmission when a signal must be transmitted through a communication channel is of essential importance in design of communication systems. When system resources are limited, such as transmission bandwidths assigned to a wireless communication channel, appropriate utility of available resources becomes imperative. This paper investigates fundamental relationships between accuracy of information exchange and communication resources, on a platform of wireless communication channels that involve typical system blocks of data compression, quantization, and stochastic wireless channels. The main complexity relationships developed in this paper provide rigorous trade-off between resource consumptions and information processing errors of each block. When these relationships are integrated, an optimization procedure emerges that allows optimal allocation of resources to each system block, such as compression ratio, quantization levels, and transmission speed, to maximize overall information accuracy. Consequently, the overall errors of the transmitted signal will be minimized at the receiver end.
It is well known that space and time complexity is one of the main bottlenecks of supervisor synthesis. The model of a large system is usually too big to be explicitly expressed, owing to composition of local componen...
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It is well known that space and time complexity is one of the main bottlenecks of supervisor synthesis. The model of a large system is usually too big to be explicitly expressed, owing to composition of local components' models, making supervisor synthesis difficult, if still possible. In this paper, we propose a distributed supervisor synthesis approach, where instead of computing a model of the entire system, a local abstraction of the system with respect to each local component is computed based on weak bisimulation. Then a local supervisor for each component is computed based on the component model and the abstract system model, by using well developed centralized supervisor synthesis approaches. The collection of all resulting local supervisors forms a distributed supervisor
In this paper, we capture the impact of an ARQ scheme in the MAC/LLC layer with a forward error-correcting code on upper-layer packet transmissions over a Markovian channel by examining the performance of a single ser...
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This paper describes the prototype Wizard's Apprentice, a computer-augmented board game. Unlike many previous examples from research, which use board games as a means to explore technology, the game was developed ...
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This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have various benefits compared with charge-couple...
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This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have various benefits compared with charge-coupled devices (CCDs), the images obtained from CISs have much lower quality than those from CCDs. To improve the quality of CIS images, it is required to do reproducing and enhancing processings such as color interpolation, white balancing, color correction, gamma correction and color conversion. They are implemented individually in most conventional designs though they have similar functional characteristics. In this proposed structure, the gamma correction block is moved to the front in order to combine several image signal processings into one block. An efficient compensation scheme is also proposed to reduce the errors caused by the moving of the non-linear gamma correction. A prototype CIS image signal processor is implemented in Verilog-HDL and synthesized with 0.18μm standard cell library. Experimental results show that the proposed structure reduces area and power consumption by 23.8% and 31.1%, respectively.
This paper proposes a robust hand-posture recognition method by learning similarity between hand-posture and structure for the performance improvement of vision-based hand-posture recognition. The difficulties in visi...
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This paper focuses on the mapping strategies in the interface design for the Expression Synthesis Project (ESP). The goal of ESP is to use the metaphor of driving to allow non-experts to interactively create expressiv...
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This paper presents a new optimization algorithm for designing parallel cyclic redundancy check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on ...
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This paper presents a new optimization algorithm for designing parallel cyclic redundancy check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead
This paper examines the mechanism of disturbance rejection in control systems employing a technique called equivalent-input-disturbance estimation. Analysis of the mechanism shows that the filter in the control system...
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This paper examines the mechanism of disturbance rejection in control systems employing a technique called equivalent-input-disturbance estimation. Analysis of the mechanism shows that the filter in the control system strongly affects the disturbance rejection performance. A new method of designing such control systems that employs H infin control theory and linear matrix inequalities is presented; and simulations of a magnetic levitation system demonstrate its validity
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